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PDF MC74VHT4051 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHT4051 | |
| Descripción | Analog Multiplexer Demultiplexer | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC74VHCT4051/D
Advance Information
www.DataSheet4U.com
Analog Multiplexer/
Demultiplexer
High–Performance Silicon–Gate CMOS
MC74VHCT4051
The MC74VHCT4051 utilizes silicon–gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF leakage currents.
This analog multiplexer/demultiplexer controls analog voltages that may
vary across the complete power supply range (from VCC to GND).
The VHCT4051 is identical in pinout to the high–speed HC4051A and the
metal–gate MC14051B. The Channel–Select inputs determine which one of
the Analog Inputs/Outputs is to be connected by means of an analog switch
to the Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
The Channel–Select and Enable inputs are compatible with TTL–type
input thresholds. The input protection circuitry on this device allows
overvoltage tolerance on the input, allowing the device to be used as a
logic–level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from
1.8V CMOS logic to 3.0V CMOS Logic while operating at the higher–voltage
power supply.
The MC74VHCT4051 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74VHCT4051 to be used to interface 5V circuits to 3V circuits.
This device has been designed so that the ON resistance (Ron) is more
linear over input voltage than Ron of metal–gate CMOS analog switches.
For a multiplexer/demultiplexer with channel–select latches, see
VHC4351.
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC74VHCTXXXXD SOIC
MC74VHCTXXXXDT TSSOP
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
• Low Noise
• In Compliance With the Requirements of JEDEC Standard No. 7A
LOGIC DIAGRAM
MC74VHCT4051
Single–Pole, 8–Position Plus Common Off
FUNCTION TABLE – MC74VHCT4051
Control Inputs
Enable
Select
CBA
ON Channels
L LLL
L LLH
L LHL
L LHH
L HLL
L HLH
L HHL
L HHH
H XXX
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
X0 13
X1 14
ANALOG
INPUTS/
OUTPUTS
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
CHANNEL
SELECT
INPUTS
A 11
B 10
C9
ENABLE 6
MULTIPLEXER/
DEMULTIPLEXER
3
X
COMMON
OUTPUT/
INPUT
PIN 16 = VCC
PIN 8 = GND
Pinout: MC74VHCT4051 (Top View)
VCC X2 X1 X0 X3 A B C
16 15 14 13 12 11 10 9
12345678
X4 X6 X X7 X5 Enable NC GND
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
10/98
© Motorola, Inc. 1998
1
REV 0
1 page  
MC74VHCT4051
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
www.DataSheet4U.com
Symbol
Parameter
Condition
BW Maximum On–Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain
or Minimum Frequency Response 0dBm at VOS; Increase fin Frequency Until dB Meter
(Figure 6)
Reads –3dB;
RL = 50Ω, CL = 10pF
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at
(Figure 7)
VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
fin = 1.0MHz, RL = 50Ω, CL = 10pF
— Feedthrough Noise.
Vin ≤ 1MHz Square Wave (tr = tf = 3ns); Adjust RL at
Channel–Select Input to Common Setup so that IS = 0A;
I/O (Figure 8)
Enable = GND
RL = 600Ω, CL = 50pF
— Crosstalk Between Any Two
Switches (Figure 12)
RL = 10kΩ, CL = 10pF
fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at
VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
fin = 1.0MHz, RL = 50Ω, CL = 10pF
THD Total Harmonic Distortion
(Figure 14)
fin = 1kHz, RL = 10kΩ, CL = 50pF
THD = THDmeasured – THDsource
VIS = 2.0VPP sine wave
VIS = 4.0VPP sine wave
VIS = 5.5VPP sine wave
* Limits not tested. Determined by design and verified by qualification.
VCC
V
3.0
4.50
6.00
3.0
4.50
6.00
3.0
4.50
6.00
3.0
4.50
6.00
3.0
4.50
6.00
3.0
4.50
6.00
3.0
4.50
6.00
3.0
4.50
6.00
Limit*
25°C
80
80
80
–50
–50
–50
–40
–40
–40
25
105
135
35
145
190
–50
–50
–50
–60
–60
–60
0.10
0.08
0.05
Unit
MHz
dB
mVPP
dB
%
250
200
125°C
150
TBD
25°C
100
– 55°C
50
0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 2.25
VIS, INPUT VOLTAGE (VOLTS)
Figure 1a. Typical On Resistance, VCC = 2.0 V
100 125°C
80 25°C
60
TBD
40 – 55°C
20
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIS, INPUT VOLTAGE (VOLTS)
Figure 1b. Typical On Resistance, VCC = 3.0 V
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
5
MOTOROLA
5 Page 
www.DataSheet4U.com
–A
–
16
1
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
9
–B
–
8
P 8 PL
0.25 (0.010) M
BM
–T
SEAT–ING
PLANE
G
K
C
D 16 PL
0.25 (0.010) M T B S A S
M
R X 45°
F
J
MC74VHCT4051
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G
1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
0.15 (0.006) T U S
16
2X L/2
L
PIN 1
IDENT.
1
0.15 (0.006) T U S
0.10 (0.004)
–T– SEATING
PLANE
D
C
16X K REF
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
0.10 (0.004) M T U S V S
A
–V–
G
NOTES:
K 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K1 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
9 PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
ÇÉÇÉJ1 GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
ÇÉÇÉ 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
B
–U– J
SECTION N–N
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
8 DIMENSION AT MAXIMUM MATERIAL CONDITION.
N
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
F C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
DETAIL E
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
–W–
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
H DETAIL E
M 0_ 8_ 0_ 8_
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
11
MOTOROLA
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MC74VHT4051.PDF ] | |
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