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PDF DS1852 Data sheet ( Hoja de datos )
| Número de pieza | DS1852 | |
| Descripción | Optical Transceiver Diagnostic Monitor | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS1852 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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DS1852
Optical Transceiver Diagnostic Monitor
www.maxim-ic.com
FEATURES
§ Implements proposals of SFF-8472 at device address A2h
[Note: requires use of external EEPROM at address
A0h for full compliance.]
§ Scaleable four-input muxing analog-to-digital converter (ADC)
Top View
§ Direct-to-digital temperature converter
A
§ Programmable alarm and warning conditions
§ Temperature-compensated, programmable three-input muxing
B
fast comparator
§ Access temperature, data, and device control through a 2-wire
C
interface
D
§ Operates from 3V or 5V supplies
§ Packaging: 25-ball BGA
E
§ Operating temperature: -40°C to +100°C
§ Programming temperature: 0°C to +70°C
§ Three levels of security
§ 127 bytes EEPROM for security level 1
1 23 45
5 x 5 BGA (0.8mm pitch)
§ 128 bytes EEPROM for security level 2
§ Address space is GBIC compliant (with use of external EEPROM at device address A0h)
ORDERING INFORMATION
DS1852B-000
25-BALL BGA
DESCRIPTION
The DS1852 transceiver monitor manages all system monitoring functions in a fiber optic data
transceiver module, in accordance with proposal SFF-8472. Its functions include 2-wire communications
with the host system, EEPROM memory for identification, tracking, and calibration, an ADC with four
muxing inputs, three fast comparators, and a temperature sensor to monitor an optical transceiver. The
DS1852 has programmable alarm and warning flags for all four analog-to-digital (A/D) conversion
values (three user analog inputs plus supply voltage) as well as the temperature. These conditions can be
used to determine critical parameters inside each module. The three fast comparators have temperature-
compensated programmability. The temperature dependencies of the trip points aid in assessing critical
conditions.
The DS1852 is offered for sale free of any royalty or licensing fees. However, users should be aware that implementation of the SFF-8472
proposed specifications may require the use of an invention covered by patent rights. Since these patents relate to the SFF-8472 specification
and not to the DS1852 itself, licensing questions should be directed to Finisar Corp.
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DS1852
ANALOG-TO-DIGITAL CONVERTER
TwhwewA.DDatCaShreeeat4dUs.caomtotal of five inputs: VCC (internal), temperature (internal), and external inputs Bin, Pin,
and Rin. All conversions are updated every 13ms (nominal) or 20ms (max) in rotation. The conversions
are absolute and compared to an internal reference. While the 16-bit values are read, only the upper 12
are significant. The lower four bits are undefined.
The temperature and analog voltage inputs are calibrated by Dallas Semiconductor and read with the
following scale:
Temperature: High byte: -128°C to +127°C signed; low byte: 1/256°C. The lower four bits
should be ignored.
S 26 25 24 23 22 21 20
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
VCC: This reads as an unsigned 16-bit quantity at 100mV LSB, with a maximum range of
6.5535V, when using the factory default value. The lower four bits should be ignored.
Bin, Pin, Rin: These read as an unsigned 16-bit quantity at 38.147mV LSB, with a maximum range
of 2.500V, when using factory default values. The lower four bits should be ignored.
215 214 213 212 211 210 29
27 26 25 24 23 22 21
28
20
Each analog input has a 16-bit scaling calibration in Table 03h EEPROM. This allows the analog
conversion values to be calibrated for full scale at any input voltage from 0.2V to 6.5535V. The ADC
conversion value will clamp rather than roll over. Each external analog channel has a maximum input
voltage of VCC independent of the calibration factor.
The upper four bits of scaling select the coarse range; the lower 12 bits are for fine adjustments. The
algorithm to trim the scale is described below.
The scaling factors for each input (VCC, VBin, VPin, and VRin) are 16 bits wide. They are located in
Table 03h at addresses C8h to CFh, respectively. The 16 bits are a combination of two trims. The lower
12 bits are binary weighted and give the high resolution trim for scaling the input to output relationship.
The upper four bits are a coarse-adjust of the lower 12 bits. In other words, the upper four bits scale the
LSB value of the binary weighted lower 12 bits.
As an illustration, assume a value of 1V is needed to read full scale. Force a voltage less than 1V
(975mV, for example) to keep clamping out of the way. The closer to max voltage the better, but not too
close.
1) Set the scale trim to 0FFFh (the upper four bits to all zeros and the lower 12 bits to all ones).
2) Use a SAR approach on the upper four bits, starting with 1000b, to find the smallest 4-bit trim
necessary to cause the voltage reading to be above the input (in this case, greater than or equal to
975mV). If they all clamp, that is okay. That means 0000b is the needed value for the upper four
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DS1852
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
wwawywt.hDaattaSthheeeSt4DU.Acomline is a stable LOW during the HIGH period of the acknowledge-related clock pulse.
Of course, setup and hold times must be taken into account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the bus will not be released.
The DS1852 may operate in the following two modes:
1) Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave (device) address and direction bit.
2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1852 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
Slave Address: Command/control byte is the first byte received following the START condition from
the master device. The command/control byte consists of a 4-bit control code. For the DS1852, this is set
as 1010 000 (when ASEL is ‘0’) binary for R/W operations. The last bit of the command/control byte
(R/W) defines the operation to be performed. When set to a 1 a read operation is selected, and when set
to a 0 a write operation is selected.
Following the START condition, the DS1852 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the chip address control code, and the R/W bit, the slave device
outputs an acknowledge signal on the SDA line.
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet DS1852.PDF ] | |
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