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PDF U9280M-H Data sheet ( Hoja de datos )
| Número de pieza | U9280M-H | |
| Descripción | Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 4-bit HARVARD Architecture
• 4k × 8-bit Application ROM
• 256 × 4-bit RAM
• 32 × 16-bit EEPROM
• 10 Bi-directional I/Os
• 4 External Interrupt Inputs (SSO20)
• 8 Interrupt Levels
• 2 × 8-bit Multifunction Timer/Counter
• Interval Timer with Watchdog
• Two-Wire Interface (TWI)
• Voltage Supervisor
• On-chip RC Oscillator
• On-chip Crystal Oscillator
Benefits
• Contactless Power Supply and Communication Interface
• Power Management for Contactless and Battery Power Supply
• Shift-register-supported Modulator and Demodulator Stages
• Low Power Consumption
• Active Mode < 300 µA at 2V and 1 MHz System Clock Frequency
(2 µs Instruction Cycle)
• Power-down Mode < 1 µA
• Supply Voltage 2.0V to 6.5V
• High-level Language Programming in qFORTH
• Operating Speed: 1 µs to 10 µs Instruction Cycle (2 µs at VDD = 2V)
1. Description
The U9280M-H IC is a multi-chip module for remote control and contactless ID sys-
tems. It consists of the ATAR092 microcontroller and U3280M transponder interface
circuit with EEPROM. A coil connected to the transponder interface serves as a wire-
less bi-directional communication interface as well as a power supply for the
microcontroller and the interface. As a transponder, the device is supplied by a mag-
netic RF field applied at the coil. For IR- or RF-transmitter applications, it can be
supplied by a battery. The microcontroller supports, with its built-in timers, a wide
range of IR- and RF-transmission modes such as burst-modulation modes, PWM-,
NRZ-, Manchester- and Bi-phase coding.
Microcontroller
with
Transponder
Interface
U9280M-H
Rev. 4591B–RFID–09/05
1 page  
U9280M-H
Figure 3-1. Block Diagram ATAR092
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V SS V DD
OSC1 OSC2
BP10
BP13
BP20/NTE
BP21
BP22
BP23
Brown-out protect
RESET
Voltage monitor
External input
VMI
Port 1
RC Crystal External
oscillators oscillators clock input
Clock management
ROM
4 K x 8-bit
RAM
256 x 4 bit
MARC4
4-bit CPU core
I/O bus
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
8/12-bit timer
with modulator
SSI
Serial interface
T2I
T2O
SD
SC
Timer 3
8-bit
timer / counter
with modulator
and demodulator
T3O
T3I
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
Data dir. +
alt. function
Port 6
BP40 BP42
BP50 BP52
INT3
T2O BP43 INT6 INT1
SC BP41
INT3
BP51 BP53
VMI SD INT6 INT1
T2I
BP60 BP63
T3O T3I
3.2 The U3280M Transponder Interface
The transponder interface contains a rectifier stage to rectify the AC from the coil inputs and to
supply itself and an additional microcontroller device with power from an LC-resonant circuit at
the coil inputs. It is also possible to supply the device via the VBatt -input with DC from a battery.
The built-in power management switches automatically between battery supply (VBatt pin) and
coil supply. It switches to coil supply if a field is applied at the coil and switches back to battery if
the field is removed.
The voltage from the coil or the VBatt pin is output at the VDD pin to supply the microcontroller
device. At the VDD pin a capacitor must be connected to smooth and buffer the supply voltage for
the transponder interface and the microcontroller. This capacitor is also used to buffer the supply
voltage during communication (damping and gaps in the field).
For communication, a damping-stage and a gap-detect circuitry is on the chip. By means of the
damping stage the coil voltage can be modulated to transmit data via the field. It can be con-
trolled with the modulator input (MOD pin) via the microcontroller. The gap detection circuitry
detects gaps in the field and outputs the gap/field signal at the gap detect output (NGAP pin). It
can be used to receive data via a modulated field and to check if a field is applied at the coil.
4591B–RFID–09/05
5
5 Page 
U9280M-H
3.9.2 Control Byte Format
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Start
EEPROM address
A4 A3
A2
A1
Mode control bits
Read/Write
A0 C1 C0
R/W Ackn
The control byte follows the start condition and consists of the 5-bit row address, 2 mode control
bits and the read/not write-bit.
3.9.3 Data Transfer Sequence
Start
Control byte
Ackn.
Data byte
Ackn.
Data byte
Ackn.
Stop
• Before the START condition and after the STOP condition the device is in standby mode and
the SDA-line is switched to input with a pull-up resistor.
• The START condition follows a control byte that determines the following operation. Bit 0 of
the control byte is used to control the following transfer direction. A 0 defines a write access
and a 1 a read access.
3.10 EEPROM
The EEPROM has a size of 512 bits and is organized as a 32 × 16-bit matrix. To read and write
data to and from the EEPROM the serial interface must be used. The interface supports one and
two byte write accesses and one to n-byte read accesses to the EEPROM.
3.10.1
Operating Modes
The operating modes of the EEPROM are defined via the control byte. The control byte contains
the row address, the mode control bits and the read/write bit that is used to control the direction
of the following transfer. A 0 defines a write access and a 1 a read access. The five address bits
select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the com-
plete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or
overwritten via the serial interface. The two mode control bits C1 and C2 define in which order
the accesses to the buffer are performed: High byte – low byte or low byte – high byte. The
EEPROM also supports autoincrement and autodecrement read operations. After sending the
start address with the corresponding mode, consecutive memory cells can be read row by row
without transmission of the row addresses.
Two special control bytes enable the complete initialization of EEPROM with a 0 or with a 1.
3.10.2
Write Operations
The EEPROM allows 8-bit and 16-bit write operations. A write access starts with the START
condition followed by a write control byte and one or two data bytes from the master. It is com-
pleted via the STOP condition from the master after the acknowledge cycle.
If the EEPROM receives the control byte, it loads the content of the addressed memory cell into
a 16-bit read/write buffer. After the first data byte has been received the EEPROM starts the
internal programming cycle. It consists of an erase cycle (write “zeros”) and the write cycle (write
“ones”). Each cycle takes about 10 ms. The write cycle is started after the stop condition and the
complete buffer is stored back automatically to the EEPROM. That means for two-byte write
operations, the second byte must be transferred within the erase cycle otherwise only the first
byte will be stored in the EEPROM and the second byte will be ignored.
4591B–RFID–09/05
11
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