|
|
PDF STMPE821 Data sheet ( Hoja de datos )
| Número de pieza | STMPE821 | |
| Descripción | 8-bit Xpander Logic | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de STMPE821 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
STMPE821
8-bit Xpander Logic™ with touchkey controller
Preliminary Data
Features
■ Up to 8 GPIOs
www.DataSheet4U■.comUp to 8 touchkey capacitive touch inputs
■ Operating voltage 1.8 - 5.5 V
■ Internal regulator
■ Interrupt output pin
■ I2C interface
■ 8 kV HBM ESD protection
■ 40 fF resolution, 128 steps capacitance
measurement (5.0 pF dynamic range)
■ Advanced data filtering (AFS)
■ Environment tracking calibration (ETC)
■ Individually adjustable touch variance (TVR)
setting for all channels
■ Adjustable environmental variance (EVR) for
optimal calibration
Applications
■ Mobile and smart phones
■ Portable media players
■ Game consoles
QFN16L
(2.6 x 1.8 mm)
Description
The STMPE821 is a GPIO (general purpose
input/output) port expander able to interface a
main digital ASIC via the two-line bidirectional bus
(I2C).
A separate GPIO expander is often used in
mobile multimedia platforms to solve the
problems of the limited amount of GPIOs typically
available on the digital engine.
The STMPE821 offers great flexibility, as each I/O
can be configured as input, output or specific
functions. The device has been designed with
very low quiescent current and includes a wakeup
feature for each I/O, to optimize the power
consumption of the device.
Table 1. Device summary
Order code
STMPE821QTR
Package
QFN16L (2.6 x 1.8 mm)
Packing
Tape and reel
June 2008
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/55
www.st.com
55
1 page  
STMPE821
1.2 Pin assignment and function
Figure 2. STMPE821 pin assignment (top view)
STMPE821 functional overview
www.DataSheet4U.com
12 11 10 9
13
14
STMPE821
15
16
1234
8
7
6
5
Table 2. Pin assignments and function
Pin number
Pin name
Description
1 GPIO_2/Touch_2 GPIO 2
2 GPIO_1/Touch_1 GPIO 1
3 GPIO_0/Touch_0 GPIO 0
4
ARef
Reference capacitor for touch sensor
5
RST
RESET (active low)
6
SDA
I2C data
7
SCL
I2C clock
8 INT INT output
9
GND
GND
10 VCC Supply voltage for I2C block
11 VIO Supply voltage for GPIO and internal regulator
12 GPIO_7/Touch_7 GPIO 7
13 GPIO_6/Touch_6 GPIO 6
14 GPIO_5/Touch_5 GPIO 5
15 GPIO_4/Touch_4 GPIO 4
16 GPIO_3/Touch_3 GPIO 3
CS00045
5/55
5 Page 
STMPE821
4 I2C interface
I2C interface
www.DataSheet4U.com
The features that are supported by the I2C interface are the following ones:
● I2C slave device
● Compliant to Philips I2C specification version 2.1
● Supports standard (up to 100 kbps) and fast (up to 400 kbps) modes.
● 7-bit and 10-bit device addressing modes
● General call
● Start/Restart/Stop
● I2C address is 0x58 (0xB0/0xB1 for write/read, including the LSB)
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and will not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.
Data Input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/WRITE bit (R/W). The bit is set to 1 for read and 0 for write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself
from the bus by not responding to the transaction.
11/55
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STMPE821.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| STMPE821 | 8-bit Xpander Logic | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |