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PDF 74V2T125 Data sheet ( Hoja de datos )
| Número de pieza | 74V2T125 | |
| Descripción | DUAL BUS BUFFER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74V2T125
DUAL BUS BUFFER (3-STATE)
s HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 1µA(MAX.) at TA=25°C
www.DataSheet4U.csomCOMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
SOT23-8L
ORDER CODES
PACKAGE
SOT23-8L
SOT323-8L
PRELIMINARY DATA
SOT323-8L
T&R
74V2T125STR
74V2T125CTR
DESCRIPTION
The 74V2T125 is an advanced high-speed CMOS
DUAL BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
tecnology.
3-STATE control input nG has to be set HIGH to
place the output into the high impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 3V to 5V systems
and it is ideal for portable applications like
personal digital assistant, camcorder and all
battery-powered equipment.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 2001
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This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.
1 page  
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74V2T125
www.DataSheet4U.com
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74V2T125.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74V2T125 | DUAL BUS BUFFER | STMicroelectronics |
| 74V2T126 | DUAL BUS BUFFER | STMicroelectronics |
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