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PDF U630H04 Data sheet ( Hoja de datos )
| Número de pieza | U630H04 | |
| Descripción | Hardstore 512x8 Nvsram | |
| Fabricantes | ZMD | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de U630H04 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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Preliminary
U630H04
HardStore 512 x 8 nvSRAM
Features
F High-performance CMOS nonvo-
latile static RAM 512 x 8 bits
F 25 and 45 ns Access Times
F 12 and 25 ns Output Enable
F Access Times
Unlimited Read and Write to
F SRAM
Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
F Automatic RECALL on Power Up
Fwww.DataSheet4HUa.crdowmare RECALL Initiation
F (RECALL Cycle Time < 20 µs)
Unlimited RECALL cycles from
EEPROM
F Single 5 V ± 10 % Operation
F Operating temperature ranges:
0 to 70°C
-40 to 85°C
F CECC 90000 Quality Standard
F ESD characterization according
MIL STD 883C M3015.7-HBM
F Packages: PDIP28 (300 mil)
PDIP28 (600 mil)
SOP28 (300 mil)
Description
The U630H04 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H04 is a fast static RAM
(25 and 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H04 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
NE
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 PDIP 22
8 SOP 21
9 20
10 19
11 18
12 17
13 16
14 15
Top View
VCC
W
n.c.
A8
n.c.
n.c.
G
n.c.
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A8
DQ0 - DQ7
E
G
W
NE
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
December 12, 1997
1
1 page  
Preliminary
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f
Ai
DQi
Output
Previos
Data Valid
1
t cR
Address Valid
2
ta(A)
9 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tv(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
Output Data
Valid
Ai
www.DataSheet4U.com
E
G
DQi
Output
ICC
High Impedance
ACTIVE
STANDBY
1
tcR
Address Valid
2
ta(A)
3
ta(E)
7
ten(E)
4
ta(G)
8
ten(G)
10
tPU
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
5
tdis(E)
6
tdis(G)
Output Data
Valid
11
tPD
U630H04
No. Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
tAVAV
tWLWH
tAVWL
tAVWH
tELWH
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tAVAV
tWLEH
tAVEL
tAVEH
tELEH
tDVEH
tEHDX
tEHAX
tcW
tw(W)
tsu(W)
tsu(A-WH)
tsu(A-WH)
tsu(E)
tw(E)
tsu(D)
th(D)
th(A)
tdis(W)
ten(W)
25
Min. Max.
45
Min. Max.
Unit
25 45 ns
20 35 ns
20 35 ns
0 0 ns
20 35 ns
20 35 ns
20 35 ns
12 20 ns
0 0 ns
0 0 ns
10 15 ns
5 5 ns
December 12, 1997
5
5 Page 
Preliminary
U630H04
Test Configuration for Functional Check
VCCt
5V
A0
A1 DQ0
A2 DQ1
480
VIH
A3
A4
DQ2
A5 DQ3
A6 DQ4
A7 DQ5
VIL
A8
DQ6
DQ7
VO
NE
E
W
G VSS
30 pF s
255
www.DataShese: t4IUn .mceoamsurement of tdis-times and ten-times the capacitance is 5 pF.
t: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Input Capacitance
Output Capacitance
VCC = 5.0 V
VI = VSS
f = 1MHz
Ta = 25 °C
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Symbol
CI
CO
Example
Type
U630H04 B D C 25
ESD Class
blank > 2000 V
B > 1000 V
Package
D = PDIP (300 mil)
D1 = PDIP (600 mil)
S = SOP (300 mil)
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
Min.
Max.
8
7
Unit
pF
pF
Access Time
25 = 25 ns
45 = 45 ns (on special request)
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indication the year, and the last 2
digits the calendar week.
December 12, 1997
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet U630H04.PDF ] | |
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