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90CR283 Datasheet PDF - National Semiconductor

Part Number 90CR283
Description DS90CR283
Manufacturers National Semiconductor 
Logo National Semiconductor Logo 

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July 2001
DS90CR283/DS90CR284
28-Bit Channel Link-66 MHz
General Description
The DS90CR283 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS link. Every
cycle of the transmit clock 28 bits of input data are sampled
and transmitted. The DS90CR284 receiver converts the
LVDS data streams back into 28 bits of CMOS/TTL data. At
www.DataSheet4U.caotmransmit clock frequency of 66 MHz, 28 bits of TTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.848 Gbit/s
(231 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data bus and one clock, up to 58 conductors are required.
With the Channel Link chipset as few as 11 conductors (4
data pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required cable
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cables’ smaller form factor.
The 28 CMOS/TTL inputs can support a variety of signal
combinations. For example, 7 4-bit nibbles or 3 9-bit (byte +
parity) and 1 control.
Features
n 66 MHz clock support
n Up to 231 Mbytes/s bandwidth
n Low power CMOS design (< 610 mW)
n Power Down mode (< 0.5 mW total)
n Up to 1.848 Gbit/s data throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS Standard
Block Diagrams
DS90CR283
DS90CR284
Order Number DS90CR283MTD
See NS Package Number MTD56
DS012889-27
DS012889-1
Order Number DS90CR284MTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation DS012889
www.national.com

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90CR283 equivalent
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RSKM
RCOP
RCOH
RCOL
RSRC
www.DataShReHetR4CU.com
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
RxIN Skew Margin (Note 7),
f = 40 MHz
VCC = 5V, TA = 25˚C (Figure 17)
RxCLK OUT Period (Figure 7)
f = 66 MHz
RxCLK OUT High Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK OUT Low Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Setup to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Hold to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK IN to RxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Power Down Delay (Figure 11)
Min Typ Max Units
2.5 4.0
ns
2.0 4.0
ns
700 ps
600 ps
15 T 50
ns
6 ns
4.3 5
ns
10.5 ns
7.0 9
ns
4.5 ns
2.5 4.2
ns
6.5 ns
4 5.2
ns
6.4 10.7 ns
10 ms
1 µs
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “WORST CASE” Test Pattern
DS012889-2
DS012889-3
FIGURE 2. DS90CR283 (Transmitter) LVDS Output Load and Transition Timing
DS012889-4
DS012889-5
FIGURE 3. DS90CR284 (Receiver) CMOS/TTL Output Load and Transition Timing
5
DS012889-6
www.national.com


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