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PDF UPD16498 Data sheet ( Hoja de datos )

Número de pieza UPD16498
Descripción 1/128 DUTY LCD CONTROLLER/DRIVER
Fabricantes NEC 
Logotipo NEC Logotipo



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No Preview Available ! UPD16498 Hoja de datos, Descripción, Manual

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16498
1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
DESCRIPTION
The µPD16498 is a controller/driver which includes display RAM for full-dot LCDs that can provide a four-level gray scale
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display. This IC is able to drive full-dot LCDs that contain up to 128 x 128 dots.
FEATURES
LCD controller/driver with on-chip display RAM
Full dot outputs: 128 segment outputs and 128 common outputs
Static icon outputs: 20 segment outputs and 2 common outputs (same signal is output)
Can operate using single power supply (logic system) in range from 1.7 to 3.6 V.
Selection of four levels of gray scales from among 33 possible levels (four-frame rate control + 8 pulse width
modulation)
Serial data input and 8-bit parallel data input (i80 series interface and M68 series interface)
Dot display RAM: 128 x 128 x 2 bits
On-chip booster: Switchable from x2 to x9 modes
Selectable bias levels: 1/12 to 1/7 bias (normal display), 1/6 or 1/5 bias (partial display)
Duty settings: 1/128 to 1/1 duty
On-chip voltage divider resistor
On-chip oscillator
ORDERING INFORMATION
Part Number
µPD16498P
µPD16498W
Package
Chip
Wafer
Remark Purchasing the chip/wafer entails the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15730EJ2V0DS00 (2nd Edition)
Date Published June 2002 NS CP(K)
2001

1 page




UPD16498 pdf
µPD16498
1. BLOCK DIAGRAM
SEG1
Data
register
SEG128
COM1
COM128
PCOM1 PCOM2
Segment driver
Common driver
Pictograph common driver
/RES
/CS1
CS2
C86
PSX
RDS
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/WR(R,/W)
P7(SI)
P6(SCL)
P5 to P0
RS
IRS
TM/S
TFR
TFRSYNC
TDOF
TSISYNC
SIGIN1
SIGIN2
TSTIFS
TSTRTST
TSTVIHL
TESTOUT
OSCIN1
OSCIN2
OSCOUT
TOSCSYNC
CLS
C1+, C1-
C9+, C9-
C1A
I/O
buffer
Segment
G/S and blink
control
Display data latch
Display data RAM
(128 x 128 x 2 bits)
Icon data RAM
(20 x 2 bits)
Address decoder
Command decoder
Register
Oscillator
circuit
Timing generator
D/A converter
DC/DC
converter
Op amp
Common
timing
generator
Pictograph
segment
driver
Pictograph
common
timing
generator
PSEG1
PSEG20
Segment
G/S and blink
timer
LCD voltage generator
VOUT VRS IRS VR AMPOUTP AMPOUT VLCD VLC1 VLC2 VLC3 VLC4
VDD1 VDD2 VSS
Remark /xxx indicates active low signals.
Data Sheet S15730EJ2V0DS
5

5 Page





UPD16498 arduino
µPD16498
3.2 Logic System Pins
Symbol
PSX
Name
Data transfer
selection
/CS1,
CS2
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(E)
Chip select
Read
(enable)
Pad No.
106, 107
112, 113,
114, 115
124, 125
/WR
(R,/W)
Write
(read/write)
122, 123
C86
Interface selection
104, 105
RDS
Data pin selection
127,128
I/O
Input
Input
Input
Input
Input
Input
(1/2)
Description
This pin is used to select between parallel data input and serial
data input.
PSX = H: Parallel data input
PSX = L: Serial data input
These pins are used for chip select signals. When /CS1 = L (CS2
= H), the chip is active and can perform data input/output
operations including command and data I/O.
When i80 series parallel data transfer (/RD) has been selected,
the signal at this pin is used to enable read operations. Data is
output to the data bus only when this pin is L.
When M68 series parallel data transfer (E) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the falling edge of this signal.
When i80 series parallel data transfer (/WR) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the rising edge of this signal.
When 68 series parallel data transfer (R,/W) has been selected,
this pin is used to determine the direction of data transfer.
L: Write
H: Read
This pin is used to switch between interface modes (i80 series
CPU or M68 series CPU).
L: Selects i80 series CPU mode
H: Selects M68 series CPU mode
This pin determines the direction of a data as follows. Fixed to
low level at the time serial data input (PSX = L).
RDS P7 P6 P5 P4 P3 P2 P1 P0
Low D7 D6 D5 D4 D3 D2 D1 D0
High D0 D1 D2 D3 D4 D5 D6 D7
P0 to P5,
Data bus
P6 (SCL)
P7 (SI)
(serial clock)
(serial input)
RS Index
register/data,
command
selection
/RES
Reset
148 to 145, 143 to 140,
138 to 135,
133, 132,
131, 130
I/O
119, 120
Input
117, 118
Input
These pins comprise an 8-bit bidirectional data bus that connects
to an 8-bit or 16-bit standard CPU bus.
When the serial interface has been selected (PSX = L), P6
functions as a serial clock input pin (SCL) and P7 functions as a
serial data input pin (SI). In either case, pins P0 to P5 are in high
impedance mode.
When the chip is not selected, P0 to P7 are in high impedance
mode.
Usually, this pin is connected to the LSB of the standard CPU
address bus and is used to distinguish between data from index
registers and data/commands.
RS = H: Indicates that data from D0 to D7 is data/command
RS = L : Indicates that data from D0 to D7 is index register
contents
When /RES is low, an internal reset is performed. The reset
operation is executed at the /RES signal level.
Data Sheet S15730EJ2V0DS
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