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PDF TH58NVG2S3BTG00 Data sheet ( Hoja de datos )
| Número de pieza | TH58NVG2S3BTG00 | |
| Descripción | 4-Gbit CMOS NAND EPROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TH58NVG2S3BTG00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M × 8 BIT) CMOS NAND E2PROM
Lead-Free
DESCRIPTION
The TH58NVG2S3B is a single 3.3 V 4Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 4096 blocks.
The device has a 2112-byte static register which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TH58NVG2S3B is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
www.DataSheet4MUem.coormy cell array
Register
Page size
Block size
TH58NVG2S3B
2112 × 128K × 8 × 2
2112 × 8
2112 bytes
(128K + 4K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Max 4096 blocks
Min 4016 blocks
• Power supply
VCC = 2.7 V to 3.6 V
• Program/Erase Cycles
100000 Cycles (With ECC)
• Access time
Cell array to register 25 µs max
Serial Read Cycle
50 ns min
• Program/Erase time
Auto Page Program
Auto Block Erase
200 µs/page typ.
1.5 ms/block typ.
• Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
10 mA typ.
10 mA typ.
10 mA typ.
100 µA max
• Package
TH58NVG2S3BTG00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)
• Lead-Free
1 2004-08-20A
1 page  
TH58NVG2S3BTG00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70 , VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
tCLS
CLE Setup Time
tCLH
CLE Hold Time
tCS CE Setup Time
tCH CE Hold Time
tWP Write Pulse Width
tALS
ALE Setup Time
tALH
ALE Hold Time
tDS Data Setup Time
tDH Data Hold Time
www.DataSheetWt4CU.com Write Cycle Time
tWH WE High Hold Time
tWW
WP High to WE Low
tRR Ready to RE Falling Edge
tRW Ready to WE Falling Edge
tRP Read Pulse Width
tRC Read Cycle Time
tREA
RE Access Time
tCEA
CE Access Time
tCLEA
CLE Access Time
tALEA
ALE Access Time
tOH Data Output Hold Time
tRHZ
RE High to Output High Impedance
tCHZ
CE High to Output High Impedance
tREH
RE High Hold Time
tIR Output-High-impedance-to- RE Falling Edge
tRHW
RE High to WE Low
tWHC
WE High to CE Low
tWHR
WE High to RE Low
tR Memory Cell Array to Starting Address
tWB WE High to Busy
tRST
Device Reset Time (Ready/Read/Program/Erase)
MIN
MAX
UNIT
0⎯
10 ⎯
0⎯
10 ⎯
25 ⎯
0⎯
10 ⎯
20 ⎯
10 ⎯
50 ⎯
15 ⎯
100 ⎯
20 ⎯
20 ⎯
35 ⎯
50 ⎯
⎯ 35
⎯ 45
⎯ 45
⎯ 45
10 ⎯
⎯ 30
⎯ 20
15 ⎯
0⎯
30 ⎯
30 ⎯
30 ⎯
⎯ 25
⎯ 200
⎯ 6/6/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
NOTES
5 2004-08-20A
5 Page 
Column Address Change in Read Cycle Timing Diagram (1/2)
TH58NVG2S3BTG00
CLE
CE
tCLS tCLH
tCS tCH
WE
tWC
tCLS tCLH
tCS tCH
tCLEA
tCEA
tALH tALS
tALH
tALS
ALE
www.DataSheReEt4U.com
tDS tDH
tR
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
tWB
tDS tDH
tRC
tRR tREA
I/O
RY / BY
00h
CA0 CA8 PA0 PA8 PA16
to 7 to 11 to 7 to 15 to 17
30h
Column address
A
Page address
P
DOUT DOUT DOUT
A A+1 A+N
Page address
P
Column address
A
1
Continues from 1 of next page
11 2004-08-20A
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TH58NVG2S3BTG00.PDF ] | |
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