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What is GD16588?

This electronic component, produced by the manufacturer "Giga", performs the same function as "(GD16584 / GD16588) Receiver / CDR and DeMUX".


GD16588 Datasheet PDF - Giga

Part Number GD16588
Description (GD16584 / GD16588) Receiver / CDR and DeMUX
Manufacturers Giga 
Logo Giga Logo 


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an Intel company
10 Gbit/s
Receiver, CDR and
DeMUX
GD16584/GD16588
(FEC)
Preliminary
General Description
Features
GD16584 and GD16588 are Receiver
chips for use in STM-64/192 and Optical
Transport Networking (OTN) systems.
The component is available in two ver-
sions:
u GD16584 for 9.5328 Gbit/s.
u GD16588 for 10.66 Gbit/s for OTN or
Forward Error Correction (FEC).
Except the different operating bit rates
the two versions are functional identical.
The receiver is a Clock and Data Reco-
very IC with:
u a low noise VCO
u a Bang-Bang Phase Detector
u a 1:16 De-multiplexer
u a Lock Detect
u a Phase and Frequency Detector.
Clock and data are regenerated by using
a Phase Locked Loop (PLL) with an ex-
ternal passive loop filter.
The VCO frequency is controlled by one
of the two Phase Detectors in order to
ensure capture and lock to the line data
rate. The Lock Detector circuit monitors
the VCO frequency and determines when
the VCO is within the lock range. When
the frequency deviates more than
500 ppm from the reference clock, it
automatically switches the phase and fre-
quency detector into the PLL loop. In the
auto lock mode the locking range is
selectable between 500 or 2000 ppm.
When the VCO frequency is within the
lock range, the Bang-Bang Phase Detec-
tor takes over. It controls the phase of
the VCO until the sampling point of data
is in the middle of the bit period, where
the eye opening is largest. A ±40 mV
Decision Threshold Control (DTC) is pro-
vided at the 10 Gbit/s input.
The 10 Gbit/s input data is sampled and
de-multiplexed by the 1:16 DeMUX. The
parallel output interface is synchronised
with the 622 MHz output clock. The clock
and data outputs are LVDS compatible.
The device operates from a dual -5.2 V
and +3.3 V power supply. The power dis-
sipation is 3.3 W, typical.
The device is manufactured in a Silicon
Bipolar process and packaged in an 132
ball 13 × 13 mm Ceramic/Plastic Ball
Grid Array (BGA).
VCTL
VCO
Timing Control
CKOUT
CKOUTN
DI
DIN
DTC
DTCN
Decision
Threshold
Control
REFCK
REFCKN
1/4
Bang
Bang
Phase
Detector
Phase
Frequency
Detector
Lock
Detect
1:16
Demultiplexer
U
D
Parallel
Output
Data
DO0
DON0
DO15
DON15
PCTL
(PHIGH)
(PLOW)
LOCK
RESET TCK
SEL3
SEL1 SEL2
VCC VDD VDDA VDDO VEE VEEA
l Complete Clock and Data Recovery
IC with auto acquisition.
l 1:16 DeMUX with differential
622 Mbit/s data outputs
l 622 MHz Clock output.
l LVDS compatible clock and data
outputs.
l OIF99.102.5 compliant timing.
l 155 or 622 MHz Reference Clock.
l Input Decision Threshold Control
(DTC): ±40 mV.
l Low noise VCO with ±5 % tuning
range.
l Dual supply operation: -5.2 V and
+3.3 V.
l Power dissipation: 3.3 W (typ).
l Silicon Bipolar technology.
l Available in three package versions:
– EB: 132 ball (16 mill) Ceramic
BGA 13 × 13 mm
– EF: 132 ball (20 mill) Ceramic
BGA 13 × 13 mm
– FB: 132 ball (20 mill) Plastic
BGA 13 × 13 mm
l Available in two versions:
– GD16584 for 10 Gbit/s
– GD16588 for 10.66 Gbit/s
Applications
l Telecommunication systems:
– SDH STM-64
– SONET OC-192.
– Optical Transport Networking
(OTN)
– FEC applications
l Fibre optic test equipment.
l Submarine systems.
Data Sheet Rev.: 12

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GD16588 equivalent
www.DAatapShpeelti4cUa.cotmions Continued
10 Gbit/s Input Interface
Postamplifier
0V
50W
GD16584/GD16588
0V
50W 50W
0/-0.4V
0/-0.4V
50W MSL
DI
DIN
>16mA
-5.2V
Figure 3. 10 Gbit/s Input (DI/DIN), DC Coupled
Post-
amplifier
GD16584/GD16588
0V
-5.2V
50W
50W
220W
DI
50W MSL 100nF DIN
220W
-5.2V
-5.2V
Figure 4. 10 Gbit/s Input (DI/DIN), AC Coupled
Data Sheet Rev.: 12
GD16584/GD16588
Page 5 of 15


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for GD16588 electronic component.


Information Total 15 Pages
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