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PDF GS8640Z18T-xxx Data sheet ( Hoja de datos )
| Número de pieza | GS8640Z18T-xxx | |
| Descripción | (GS8640ZxxT-xxx) 72Mb Pipelined and Flow Through Synchronous NBT SRAM | |
| Fabricantes | GSI Technology | |
| Logotipo |  |
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GS8640Z18/36T-300/250/200/167
100-Pin TQFP
Commercial Temp
Industrial Temp
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–167 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8640Z18/36T is a 72Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8640Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8640Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Parameter Synopsis
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-300 -250 -200 -167 Unit
2.3 2.5 3.0 3.5 ns
3.3 4.0 5.0 6.0 ns
400 340 290 260 mA
480 410 350 305 mA
5.5 6.5 7.5 8.0 ns
5.5 6.5 7.5 8.0 ns
285 245 220 210 mA
330 280 250 240 mA
*All GSI Technology packages are at least 5/6 RoHS compliant.
Packages listed with the additional “G” designator are 6/6 RoHS compliant.
Rev: 1.01 1/2006
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
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GS8640Z18/36T-300/250/200/167
GS8640Z18/36 NBT SRAM Functional Block Diagram
Rev: 1.01 1/2006
5/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
5 Page 
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GS8640Z18/36T-300/250/200/167
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ H
Active
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
SCD
L
H or NC
Dual Cycle Deselect
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
H or NC
High Drive (Low Impedance)
Low Drive (High Impedance)
9th Bit Enable
L Activate DQPx I/Os (x18/x3672 mode)
PE
H or NC
Deactivate DQPx I/Os (x16/x3272 mode)
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those this input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Rev: 1.01 1/2006
11/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
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