PDF UC62LS4008 Data sheet ( Hoja de datos )

Número de pieza	UC62LS4008
Descripción	Low Power CMOS SRAM 512K X 8 Bits
Fabricantes	ETC
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No Preview Available ! www.DataSheet4U.com Low Power CMOS SRAM 512K X 8 Bits UC62LS4008 -20/-25 Features: • Vcc operation voltage : 3.0V ~ 3.6V • Low power consumption : 20mA (Max.) operating current 2uA (Typ.) CMOS standby current • High Speed Access time : 25ns (Max.) at Vcc = 3.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Data retention supply voltage as low as 1.2V • Easy expansion with CE\ and OE\ options Description The UC62LV2008 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from 3.0V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 2uA and maximum access time of 25ns in 3.0V operation. Easy memory expansion is provided enable (CE\), and active LOW output enable (OE\) and three-state output drivers. The UC62LS4008 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The UC62LS4008 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx20.0mm TSOP (type I), and 8mmx13.4mm STSOP. PRODUCT FAMILY Product Family Operating Tempature UC62LS4008HC UC62LS4008FC UC62LS4008GC UC62LS4008AC UC62LS4008HI UC62LS4008FI UC62LS4008GI UC62LS4008AI 0 ~ 70 -40 ~ 85 Vcc Range 3.0V ~ 3.6V 3.0V ~ 3.6V Speed (ns) Vcc=3.0V(Max.) 20/25 20/25 Power Consumption STANDBY Operating Vcc=3.3V(Typ.) Vcc=3.6V(Max.) 2uA 20mA 2uA 20mA Package Type TSOP-32 SOP-32 STSOP-32 DICE TSOP-32 SOP-32 STSOP-32 DICE PIN CONFIGURATIONS A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 CS62LS4008FI 24 10 CS62LS4008FC 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 A11 1 A9 2 A8 3 A13 4 WE 5 A18 6 CS62LS4008HI A15 7 VCC 8 CS62LS4008HC A17 9 CS62LS4008GI A16 10 A14 11 CS62LS4008GC A12 12 A7 13 A6 14 A5 15 A4 16 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 BLOCK DIAGRAM CE WE OE ROW Address COL Address CE WE OE MEMORY ARRAY 512K X 8 Bits COLUMN DECODER SENSE AMPLIFIER & WRITE DRIVER X8 I/O BUFFER U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 1 1 page www.DataSheet4U.com Low Power CMOS SRAM 512K X 8 Bits SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) ADDRESS DOUT tRC tOH tAA UC62LS4008 -20/-25 tOH READ CYCLE2 (1,3,4) CE DOUT READ CYCLE3 (1,4) tCLZ(5) ADDRESS OE CE DOUT tOLZ tCLZ(5) tCE tRC tAA tOE tCE tCHZ(5) tOH tOHZ(1,5) tCHZ(5) NOTES: 1. WE\ is high in read cycle. 2. Device is continuously selected when CE\ = VIL 3. Address valid prior to or coincident with CE\ transition low. 4. OE\ = VIL. 5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 5 5 Page www.DataSheet4U.com Low Power CMOS SRAM 512K X 8 Bits Unit Symbol A A1 A2 b b1 c c1 D E E1 e L L1 y Inch 0.007 0.009 0.1055 0.014 ~ 0.014 ~ 0.006 ~ 0.012 0.006 ~ 0.011 0.805 0.445 0.555 0.050 0.033 0.055 0.004 Max 0” ~ 10” 32 mm 0.229 0.35 ~ 0.15 ~ 0.32 0.15 ~ 0.28 14.097 0.834 0.1 Max 0” ~ 10” 17 UC62LS4008 -20/-25 "A" 1 e 16 b D Seating Plane "y" SOP - 32 A (4X) A L L1 DETAIL "A" (2:1) WITH PLATING c c1 BASE METAL b b1 SECTION A-A U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 11 11 Page

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