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PDF GS1559 Data sheet ( Hoja de datos )
| Número de pieza | GS1559 | |
| Descripción | HD-LINX-TM II Multi-Rate Deserializer | |
| Fabricantes | Gennum Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de GS1559 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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GS1559 HD-LINX™ II
Multi-Rate Deserializer with
Loop-Through Cable Driver
GS1559 Data Sheet
Key Features
• SMPTE 292M and SMPTE 259M-C compliant
descrambling and NRZI → NRZ decoding (with
bypass)
• DVB-ASI sync word detection and 8b/10b decoding
• auto-configuration for HD-SDI, SD-SDI and
DVB-ASI
• serial loop-through cable driver output selectable as
reclocked or non-reclocked
• dual serial digital input buffers with 2 x 1 mux
• integrated serial digital signal termination
• integrated reclocker
• automatic or manual rate selection / indication
(HD/SD)
• descrambler bypass option
• user selectable additional processing features
including:
• CRC, TRS, ANC data checksum, line number
and EDH CRC error detection and correction
• programmable ANC data detection
• illegal code remapping
• internal flywheel for noise immune H, V, F
extraction
• FIFO load Pulse
• 20-bit / 10-bit CMOS parallel output data bus
• 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital output
• automatic standards detection and indication
• 1.8V core power supply and 3.3V charge pump
power supply
• 3.3V digital I/O supply
• JTAG test interface
• Available in a Pb-free package
• small footprint (11mm x 11mm)
Applications
• SMPTE 292M Serial Digital Interfaces
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS1559 is a reclocking deserializer with a serial
loop-through cable driver. When used in conjunction
with the GS1574 Automatic Cable Equalizer and the
GO1525 Voltage Controlled Oscillator, a receive
solution can be realized for HD-SDI, SD-SDI and
DVB-ASI applications.
In addition to reclocking and deserializing the input data
stream, the GS1559 performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 292M/259M-C, and word
alignment when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will word align
the data to K28.5 sync characters and 8b/10b decode
the received stream.
Two serial digital input buffers are provided with a 2x1
multiplexer to allow the device to select from one of two
serial digital input signals.
The integrated reclocker features a very wide Input
Jitter Tolerance of ±0.3 UI (total 0.6 UI), a rapid
asynchronous lock time, and full compliance with
DVB-ASI data streams.
An integrated cable driver is provided for serial input
loop-through applications and can be selected to output
either buffered or reclocked data. This cable driver also
features an output mute on loss of signal, high
impedance mode, adjustable signal swing, and
automatic dual slew-rate selection depending on
HD/SD operational requirements.
The GS1559 also includes a range of data processing
functions such as error detection and correction,
automatic standards detection, and EDH support. The
device can also detect and extract SMPTE 352M
payload identifier packets and independently identify
the received video standard. This information is read
from internal registers via the host interface port.
Line-based CRC errors, line number errors, TRS errors,
EDH CRC errors and ancillary data checksum errors
can all be detected. A single ‘DATA_ERROR’ pin is
provided which is a logical 'OR'ing of all detectable
errors. Individual error status is stored in internal
‘ERROR_STATUS’ registers.
Finally, the device can correct detected errors and
insert new TRS ID words, line-based CRC words,
ancillary data checksum words, EDH CRC words, and
line numbers. Illegal code re-mapping is also available.
All processing functions may be individually enabled or
disabled via host interface control.
30572 - 4 July 2005
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1 page  
1. Pin Out
GS1559 Data Sheet
1.1 Pin Assignment
1 2 3 4 5 6 7 8 9 10
A LF
VCO_
VCC
VCO_
GND
VCO
VCO
NC PCLK IO_VDD DOUT18 DOUT19
B LB_
CP_CAP CP_VDD CP_GND CONT
NC
NC FW_EN/ IO_GND DOUT16 DOUT17
/DIS
C BUFF PD_VDD PD/BUFF
_VDD
_GND
NC
NC
MASTER/
RC_BYP
YANC DOUT14 DOUT15
SLAVE
D DDI1
NC
NC IP_SEL DVB_ASI LOCKED NC
CANC DOUT12 DOUT13
E DDI1 TERM1 NC
SD/HD
CORE
_GND
CORE
_VDD
NC IO_VDD DOUT10 DOUT11
F CD1
NC
NC
20bit/ CORE CORE NC IO_GND DOUT8 DOUT9
10bit _GND _VDD
G DDI2
NC
NC
IOPROC SMPTE_ RESET
_EN/DIS BYPASS _TRST
NC FIFO_LD DOUT6 DOUT7
H DDI2 TERM2 NC
CS_
TMS
SCLK
_TCK
SDOUT DATA_
_TDO ERROR
H
DOUT4 DOUT5
J CD2
NC
NC
NC
SDO_EN
/DIS
SDIN
_TDI
K RSET CD_VDD SDO
SD0 CD_GND JTAG/
HOST
V IO_GND DOUT2 DOUT3
F IO_VDD DOUT0 DOUT1
30572 - 4 July 2005
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5 Page 
GS1559 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
F4
F10, F9,
G10, G9,
H10, H9,
J10, J9,
K10, K9
G1, H1
Name
20bit/10bit
DOUT[9:0]
DDI2, DDI2
Timing
Type Description
Non
Synchronous
Synchronous
with PCLK
Analog
Input
Output
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the output data bus width in SMPTE or Data-Through
modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel output will be 20-bit demultiplexed data.
When set LOW, the parallel outputs will be 10-bit multiplexed data.
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DOUT9 is the MSB and DOUT0 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Chroma data output in SMPTE mode
SMPTE_BYPASS =HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
Forced LOW in all modes.
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Chroma data output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Forced LOW in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
Forced LOW in all modes.
Differential input pair for serial digital input 2.
30572 - 4 July 2005
11 of 74
11 Page | ||
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| PDF Descargar | [ Datasheet GS1559.PDF ] | |
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