U632H64 Datasheet PDF - Simtek
Part Number | U632H64 | |
Description | PowerStore 8K x 8 nvSRAM | |
Manufacturers | Simtek | |
Logo | ||
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Not Recommended For New Designs
U632H64
PowerStore 8K x 8 nvSRAM
Features
High-performance CMOS non-
volatile static RAM 8192 x 8 bits
25 ns Access Time
12 ns Output Enable Access
Time
ICC = 15 mA at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
Unlimited RECALL cycles from
EEPROM
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
QS 9000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HB
(classification see IC Code
Numbers)
RoHS compliance and Pb- free
Package: SOP28 (330 mil)
Description
The U632H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U632H64 is a fast static RAM
(25 ns), with a nonvolatile electri-
cally erasable PROM (EEPROM)
element incorporated in each static
memory cell. The SRAM can be
read and written an unlimited num-
ber of times, while independent
nonvolatile data resides in
EEPROM. Data transfers from the
SRAM to the EEPROM (the
STORE operation) take place auto-
matically upon power down using
charge stored in an external 100
μF capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U632H64 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
VCAP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8 SOP
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCCX
W
HSB
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
August 15, 2006
STK Control #ML0047
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
1 Rev 1.1
|
|
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
U632H64
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
High Impedance
ten(G) (8)
ACTIVE
tPU (10)
STANDBY
tPD (11)
tdis(E) (5)
tdis(G) (6)
Output Data Valid
No.
Switching Characteristics
Write Cycle
Symbol
Alt. #1 Alt. #2 IEC
Unit
Min. Max.
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
tAVAV
tWLWH
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
tAVWL
tAVWH
tELWH
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tAVAV
tWLEH
tAVEL
tAVEH
tELEH
tDVEH
tEHDX
tEHAX
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
tsu(D)
th(D)
th(A)
tdis(W)
ten(W)
25
20
20
0
20
20
20
12
0
0
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
August 15, 2006
STK Control #ML0047
5
Rev 1.1
Preview 5 Page |
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Information | Total 15 Pages | |
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