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ISL12024 Datasheet PDF - Intersil Corporation

Part Number ISL12024
Description Real-Time Clock/Calendar
Manufacturers Intersil Corporation 
Logo Intersil Corporation Logo 

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ISL12024 datasheet, circuit
®
Data Sheet
New Features
October 18, 2006
ISL12024
FN6370.1
Real-Time Clock/Calendar with Embedded
Unique ID
The ISL12024 device is a micro-power real-time clock with
embedded 64-bit unique ID, timing and crystal
compensation, clock/calender, power-fail indicator, two
periodic or polled alarms, intelligent battery backup
switching, and integrated 512 x 8-bit EEPROM configured in
16 Bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
TEMP
NUMBER
PART
VDD RANGE
PKG.
(Note) MARKING RANGE (°C) PACKAGE DWG. #
ISL12024IBZ 12024IBZ 2.7V to -40 to +85 8 Ld SOIC M8.15
5.5V
(Pb-free)
ISL12024IVZ 2024IVZ
www.DataSheet4U.com
2.7V to -40 to +85 8 Ld TSSOP M8.173
5.5V
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Add “-T” suffix for tape and reel.
Pinouts
X1
X2
IRQ/FOUT
GND
ISL12024
(8 LD SOIC)
TOP VIEW
18
27
36
45
VDD
VBAT
SCL
SDA
VBAT
VDD
X1
X2
ISL12024
(8 LD TSSOP)
TOP VIEW
18
27
36
45
SCL
SDA
GND
IRQ/FOUT
Features
• Real-Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
- 3 Selectable Frequency Outputs
• 64-bit Unique ID
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512 x 8 Bits of EEPROM
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
• I2C Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
- Pin-compatible with the ISL12026
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Audio Video Equipment
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Computer Products
• Security Related Application
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
BlockLock is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL12024 equivalent
ISL12024
AC Electrical Specifications (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
tDH Output Data Hold Time
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip.
0
10
ns
400 pF
Cpin SDA, and SCL Pin Capacitance
10 pF
tWC Non-volatile Write Cycle Time
12 20 ms
NOTES:
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), VBAT 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
Timing Diagrams
Bus Timing
tF
tHIGH
tLOW
tR
tHD:STO
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
Write Cycle Timing
SCL
SDA
8TH BIT OF LAST BYTE
ACK
STOP
CONDITION
tWC
START
CONDITION
5 FN6370.1
October 18, 2006

5 Page
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Information Total 25 Pages
Download[ ISL12024.PDF Datasheet ]

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