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ISL22349 Datasheet PDF - Intersil Corporation

Part Number ISL22349
Description Dual Digitally Controlled Potentiometers
Manufacturers Intersil Corporation 
Logo Intersil Corporation Logo 

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ISL22349 datasheet, circuit
ISL22349
® Quad Digitally Controlled Potentiometers (XDCP™)
Data Sheet
September 15, 2006
FN6331.2
Low Noise, Low Power, I2C® Bus, 128 Taps,
Wiper Only
The ISL22349 integrates four digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
Pinout
www.DataSheet4U.com
ISL22349
(14 LD TSSOP)
TOP VIEW
RW3
A2
SCL
SDA
GND
RW2
RW1
1
2
3
4
5
6
7
14 RW0
13 SHDN
12 VCC
11 NC
10 A1
9 A0
8 NC
Features
• Four potentiometers in one package
• 128 resistor taps
• I2C serial interface
- Three address pins, up to eight devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70typical
• Shutdown mode
• Shutdown current 6.5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10ktotal resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T < +55°C
• 14 Ld TSSOP
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(k)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22349UFV14Z
(Notes 1, 2)
22349 UFVZ
50
-40 to +125
14 Ld TSSOP
M14.173
(Pb-Free)
ISL22349WFV14Z
(Notes 1, 2)
22349 WFVZ
10
-40 to +125
14 Ld TSSOP
M14.173
(Pb-Free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL22349 equivalent
ISL22349
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5) MAX
SERIAL INTERFACE SPECS
VIL A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3 0.3*VCC
VIH A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
VCC+0.3
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*
VCC
0
0.4
Cpin A2, A1, A0, SHDN, SDA, and SCL Pin
(Note 13) Capacitance
10
fSCL
tsp
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
400
50
tAA
tBUF
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until
Valid
SDA exits the 30% to 70% of VCC window
Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
900
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO
tHD:STO
tDH
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
or Volatile Only Write
both crossing 70% of VCC
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
600
1300
0
tR SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
tF SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
10 400
Rpu SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF
Off-chip
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
tSU:A A2, A1 and A0 Setup Time
Before START condition
600
UNIT
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
k
ns
5 FN6331.2
September 15, 2006

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Information Total 12 Pages
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