|
|
PDF U6808B Data sheet ( Hoja de datos )
| Número de pieza | U6808B | |
| Descripción | Specia Fail-safe IC | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de U6808B (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
Features
• Digital Self-supervising Watchdog with Hysteresis
• One 250-mA Output Driver for Relay
• Enable Output Open Collector 8 mA
• Over/Undervoltage Detection
• ENABLE and RELAY Outputs Protected Against Standard Transients
and 40V Load Dump
• ESD Protection According to MIL-STD-883 D Test Method 3015.7
– Human Body Model: ±2 kV (100 pF, 1.5 kΩ)
– Machine Model: ±200 V (200 pF, 0Ω)
1. Description
The U6808B is designed to support the fail-safe function of a safety critical system
(e.g., ABS). It includes a relay driver, a watchdog controlled by an external R/C-net-
work and a reset circuit initiated by an over and undervoltage condition of the 5-V
supply providing a low-level reset signal.
Figure 1-1. Block Diagram
VS
Bandgap
reference
+ 2.44 V
-
+
-
Power-on
reset
Reset
debounce
VS
www.DataSheet4U.com
Reset
delay
RESET
RELAY
Special
Fail-safe IC
U6808B
Under/ overvoltage
detection
RIN
WDI
ENABLE
-
+
Internal
oscillator
Current
limitation
+
-
Watchdog
RC
oscillator
GND
WDC
Rev. 4707B–AUTO–10/05
1 page  
U6808B
5.5 RESET Input
During power-on and under/overvoltage detection a reset signal is fed to this pin. It resets the
watchdog timer and sets the initial state.
5.6 WD-OK Output
After the up/down counter is incremented to status 3 (see Figure 5-2) the RS flip-flop is set and
the WD-OK output becomes logic 1. This information is available for the microcontroller at the
open-collector output ENABLE. If on the other hand the up/down counter is decremented to 0
the RS flip-flop is reset, the WD-OK output and the ENABLE output are disabled. The WD-OK
output also controls a dual MUX stage which shifts the time window by one clock after a suc-
cessful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the
trigger signal good or false. The WD-OK signal is also reset in case the watchdog counter is not
reset after 250 clocks (missing trigger signal).
5.7 Watchdog State Diagram
Figure 5-2.
Watchdog State Diagram
Initial status
1/NF
bad
bad
O/F
bad
good
1/F
good
bad
bad
good
2/NF
good
good
bad
3/NF
good
2/F
5.8 Explanation
In each block, the first character represents the state of the counter. The second notation indi-
cates the fault status of the counter. A fault status is indicated by an F and a no fault status is
indicated by an NF. When the watchdog is powered up initially, the counter starts out at the 0/F
block (initial state). Good indicates that a pulse has been received whose width resides within
the timing window. Bad indicates that a pulse has been received whose width is either too short
or too long.
4707B–AUTO–10/05
5
5 Page 
Figure 9-3. Overvoltage Condition
Overvoltage condition
> 120 µs
5V
VS
0V
> 5.6 V
V Batt
RELAY
0V
5V
ENABLE
0V
5V
RESET
0V
Reset debounce time
1st Reset delay
< 120 µs
> 5.6 V
3 good WDI pulses
2nd Reset delay
Figure 9-4. Undervoltage Condition
Undervoltage condition
> 120 µs
5V
VS
0V
< 4.5 V
V Batt
RELAY
0V
5V
ENABLE
0V
5V
RESET
0V
Reset debounce time
1st Reset delay
< 120 µs
< 4.5 V
3 good WDI pulses
2nd Reset delay
4707B–AUTO–10/05
U6808B
Don't care
Don't care
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet U6808B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| U6808B | Specia Fail-safe IC | ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |