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PDF SY58604U Data sheet ( Hoja de datos )
| Número de pieza | SY58604U | |
| Descripción | LVPECL Buffer | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY58604U
3.2Gbps Precision, LVPECL Buffer with
Internal Termination and Fail Safe Input
General Description
The SY58604U is a 2.5/3.3V, high-speed, fully
differential LVPECL buffer optimized to provide less
than 10pspp total jitter. The SY58604U can process
clock signals as fast as 2.5GHz or data patterns up to
Features
• Precision 800mV LVPECL buffer
Precision Edge®
3.2Gbps.
• Guaranteed AC performance over temperature and
The differential input includes Micrel’s unique, 3-pin
voltage:
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVpp) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
– DC-to > 3.2Gbps throughput
– <350ps typical propagation delay (IN-to-Q)
– <110ps rise/fall times
• Fail Safe Input
voltage reference (VREF-AC) is provided to bias the VT pin.
The output is 800mV LVPECL, with extremely fast
– Prevents output from oscillating when input is
invalid
rise/fall times guaranteed to be less than 110ps.
• Ultra-low jitter design
The SY58604U operates from a 2.5V ±5% supply or
– <1psRMS cycle-to-cycle jitter
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total jitter
random jitter
deterministic jitter
LVPECL output
is part of Micrel’s high-speed, Precision Edge® product • 2.5V ±5% or 3.3V ±10% power supply operation
line. • Industrial temperature range: –40°C to +85°C
Data sheets and support documentation can be found
on Micrel’s web site at: www.micrel.com.
• Available in 8-pin (2mm x 2mm) MLF® package
Applications
Functional Block Diagram
• All SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
• Backplane distribution
Markets
• Storage
• ATE
• Test and measurement
• Enterprise networking equipment
• High-end servers
• Access
• Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2006
M9999-092606-A
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58604U
AC Electrical Characteristics
VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V, Input tr/tf: <300ps; TA = –40°C to +85°C, unless otherwise
stated.
Symbol
fMAX
tPD
tSkew
tJitter
tr, tf
Parameter
Maximum Frequency
Propagation Delay
IN-to-Q
Part-to-Part Skew
Data
Random Jitter
Deterministic Jitter
Clock
Cycle-to-Cycle Jitter
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Duty Cycle
Condition
NRZ Data
VOUT > 400mV
VIN: 100mV-200mV
VIN: 200mV-800mV
Note 7
Note 8
Note 9
Note 10
Note 11
At full output swing.
Differential I/O
Clock
Min
3.2
2.5
180
150
40
47
Typ
4.25
3
320
230
75
Max
450
350
135
1
10
1
10
110
53
Units
Gbps
GHz
ps
ps
ps
psRMS
psPP
psRMS
psPP
ps
%
Notes:
7. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
8. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
9. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
10. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
11. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
September 2006
5 M9999-092606-A
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input Interface Applications
SY58604U
Figure 4a. CML Interface
(DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
September 2006
11 M9999-092606-A
[email protected] or (408) 955-1690
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SY58604U.PDF ] | |
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