A3950 Datasheet PDF - Allegro MicroSystems
Part Number | A3950 | |
Description | DMOS Full-Bridge Motor Driver | |
Manufacturers | Allegro MicroSystems | |
Logo | ||
There is a preview and A3950 download ( pdf file ) link at the bottom of this page. Total 12 Pages |
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DMOS Full-Bridge Motor Driver
Features and Benefits
▪ Low RDS(on) outputs
▪ Overcurrent protection
▪ Motor lead short-to-supply protection
▪ Short-to-ground protection
▪ Sleep function
▪ Synchronous rectification
▪ Diagnostic output
▪ Internal undervoltage lockout (UVLO)
▪ Crossover-current protection
Packages:
Package LP, 16 pin TSSOP
with Exposed Thermal Pad
Package EU, 16 pin QFN
with Exposed Thermal Pad
Description
Designed for PWM (pulse width modulated) control of dc
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-to-
supply / short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of VBB and VCP, and crossover-current
protection.
TheA3950 is supplied in a thin profile (<1.2 mm overall height)
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
www.DataSheet4U.com
Approximate Scale 1:1
Typical Application Diagrams
VDD
5 kΩ
0.22 μF
25 V
VBB
0.1 μF
50 V
PHASE
GND
GND
SLEEP
ENABLE
A3950
EU Package
CP2
CP1
OUTB
0.1 μF
50 V
100 μF
50 V
0.1 μF
50 V
Package EU
VDD
5 kΩ
NFAULT
MODE
PHASE
GND
SLEEP
A3950
LP Package
ENABLE
OUTA
SENSE
NC
VREG
VCP
GND
CP2
CP1
OUTB
VBB
VBB
0.22 μF
25 V
0.1 μF
50 V
0.1 μF
50 V
100 μF
50 V
0.1 μF
50 V
Package LP
A3950DS, Rev. 4
|
|
A3950
SLEEP
ENABLE
PHASE
MODE
VBB
VOUTA
0
VBB
VOUTB
0
DMOS Full-Bridge Motor Driver
Timing Diagram: PWM Control
IOUTX 0
A
1
2 34
5
15
VBB
OutA
3
24
OutB
OutA
A Charge pump and VREG power-on delay (≈200 μs)
6 789
VBB
6
7
OutB
8
9
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for A3950 electronic component. |
Information | Total 12 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ A3950.PDF Datasheet ] |
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Featured Datasheets
Part Number | Description | MFRS |
A3950 | The function is DMOS Full-Bridge Motor Driver. Allegro MicroSystems | |
A3951 | The function is FULL-BRIDGE PWM MOTOR DRIVER. Allegro MicroSystems | |
A3951SB | The function is FULL-BRIDGE PWM MOTOR DRIVER. Allegro MicroSystems | |
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