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PDF MC74HC4020A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC4020A | |
| Descripción | 14-Stage Binary Ripple Counter High-Performance Silicon-Gate CMOS | |
| Fabricantes | ON Semiconductor | |
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MC74HC4020A
14−Stage Binary Ripple
Counter
High−Performance Silicon−Gate CMOS
The MC74C4020A is identical in pinout to the standard CMOS
MC14020B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master−slave flip−flops with 12 stages
brought out to pins. The output of each flip−flop feeds the next and the
frequency at each output is half of that of the preceding one. Reset is
asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4020A for some designs.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• Pb−Free Packages are Available*
16
1
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MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC4020AN
AWLYYWWG
1
16
1
16
1
SOIC−16
D SUFFIX
CASE 751B
16
HC4020AG
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HC40
20A
ALYWG
G
1
16
1
SOEIAJ−16
F SUFFIX
CASE 966
16
74HC4020A
ALYWG
1
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 4
1
Publication Order Number:
MC74HC4020A/D
1 page  
MC74HC4020A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V −55 to 25°C ≤85°C ≤125°C Unit
trec Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0 30
3.0 20
4.5 5
6.0 4
40 50 ns
25 30
8 12
69
tw Minimum Pulse Width, Clock
(Figure 1)
2.0 70
3.0 40
4.5 15
6.0 13
80 90 ns
45 50
19 24
16 20
tw Minimum Pulse Width, Reset
(Figure 2)
2.0 70
3.0 40
4.5 15
6.0 13
80 90 ns
45 50
19 24
16 20
tr, tf Maximum Input Rise and Fall Times
(Figure 1)
2.0 1000 1000 1000 ns
3.0 800
800 800
4.5 500
500 500
6.0 400
400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negative−edge triggering clock input. A high−to−low
transition on this input advances the state of the counter.
Reset (Pin 11)
Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.
OUTPUTS
Q1, Q4—Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3)
Active−high outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING WAVEFORMS
Clock
Q1
tf
90%
50%
10%
tw
90%
50%
10%
tPLH
tTLH
tr
1/fMAX
tPHL
tTHL
VCC
GND
Clock
Reset
Any Q
50%
trec
tw
50%
tPHL
50%
VCC
GND
VCC
GND
Figure 3.
Figure 4.
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