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PDF MC74HC4046A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC4046A | |
| Descripción | Phase-Locked Loop | |
| Fabricantes | ON Semiconductor | |
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MC74HC4046A
Phase-Locked Loop
High−Performance Silicon−Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phase−locked loop contains three phase
comparators, a voltage−controlled oscillator (VCO) and unity gain
op−amp DEMOUT. The comparators have two common signal inputs,
COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self−bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1OUT and
maintains 90 degrees phase shift at the center frequency between
SIGIN and COMPIN signals (both at 50% duty cycle). Phase
comparator 2 (with leading−edge sensing logic) provides digital error
signals PC2OUT and PCPOUT and maintains a 0 degree phase shift
between SIGIN and COMPIN signals (duty cycle is immaterial). The
linear VCO produces an output signal VCOOUT whose frequency is
determined by the voltage of input VCOIN signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
op−amp output DEMOUT with an external resistor is used where the
VCOIN signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all op−amps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
• Output Drive Capability: 10 LSTTL Loads
• Low Power Consumption Characteristic of CMOS Devices
• Operating Speeds Similar to LSTTL
• Wide Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 mA Maximum (except SIGIN and COMPIN)
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Low Quiescent Current: 80 mA Maximum (VCO disabled)
• High Noise Immunity Characteristic of CMOS Devices
• Diode Protection on all Inputs
• Chip Complexity: 279 FETs or 70 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
PCPout
PC1out
COMPin
VCOout
INH
C1A
C1B
GND
1
2
3
4
5
6
7
8
16 VCC
15 PC3out
14 SIGin
13 PC2out
12 R2
11 R1
10 DEMout
9 VCOin
MARKING DIAGRAMS
16
HC4046AG
AWLYWW
1
SOIC−16
16
HC40
46A
ALYWG
G
1
TSSOP−16
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 11
1
Publication Order Number:
MC74HC4046A/D
1 page  
MC74HC4046A
[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
RS Resistor Range
VOFF
Offset Voltage
VCOIN to VDEMOUT
RD Dynamic Output
Resistance at DEMOUT
Test Conditions
At RS > 300 kW the
Leakage Current can
Influence VDEMOUT
Vi = VVCOIN = 1/2 VCC;
Values taken over RS
Range.
VDEMOUT = 1/2 VCC
Guaranteed Limit
–55 to 25_C
VCC
≤ 85°C
≤ 125°C
V Min Max Min Max Min Max Unit
3.0 50 300
4.5 50 300
6.0 50 300
kW
3.0 See Figure 13 mV
4.5
6.0
3.0 Typical 25 W
4.5
6.0
W
SWITCHING WAVEFORMS
SIGIN, COMPIN
INPUTS
50%
tPHL
PCPOUT, PC1OUT
PC3OUT
OUTPUTS
tTHL
90%
50%
10%
Figure 1.
VCC
SIGIN
INPUT
50%
GND
tPLH COMPIN
INPUT
50%
tPZH tPHZ
PC2OUT
OUTPUT
tTLH
50%
90%
Figure 2.
VCC
GND
VCC
GND
VOH
HIGH
IMPEDANCE
SIGIN
INPUT
50%
COMPIN
INPUT
50%
tPZL
PC2OUT
OUTPUT
50%
tPLZ
10%
Figure 3.
VCC
GND
VCC
GND
HIGH
IMPEDANCE
VOL
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*INCLUDES ALL PROBE AND JIG CAPACITANCE
Figure 4. Test Circuit
http://onsemi.com
5
5 Page 
MC74HC4046A
106 CL = 50 pF; R2 = ∞; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;
VVCOIN = 1/3 VCC FOR VCC = 3.0 V; Tamb = 25°C
106 CL = 50 pF; R1 = ∞; VVCOIN = 0 V; Tamb = 25°C
105
104
103
100
101 102
R1 (kW)
VCC = 6.0 V, C1 = 40 pF
VCC = 6.0 V, C1 = 1.0 mF
105
VCC = 4.5 V, C1 = 40 pF
VCC = 4.5 V, C1 = 1.0 mF
VCC = 3.0 V, C1 = 40 pF
VCC = 3.0 V, C1 = 1.0 mF
103
104
103
100
Figure 16. Power Dissipation versus R1
VCC = 6.0 V, C1 = 40 pF
VCC = 6.0 V, C1 = 1.0 mF
VCC = 3.0 V, C1 = 1.0 mF
101
VCC = 4.5 V, C1 = 40 pF
VCC = 4.5 V, C1 = 1.0 mF
VCC = 3.0 V, C1 = 40 pF
102
R2 (kW)
103
Figure 17. Power Dissipation versus R2
103
R1 = R2 = ∞; Tamb = 25°C
102
101
100
101
VCC=6.0 V
VCC=4.5 V
VCC=3.0 V
102
RS (kW)
103
Figure 18. DC Power Dissipation of
Demodulator versus RS
108 VCC =
6.0 V
107
4.5 V
3.0 V
6.0 V
4.5 V
106 3.0 V
6.0 V
4.5 V
3.0 V
105
104
INH = GND; Tamb = 25°C; R2 = ∞; VVCOIN = 1/3 VCC
R1=3.0 kW
R1=100 kW
103
R1=300 kW
102
101
102 103 104
C1 (pF)
105 106
Figure 19. VCO Center Frequency versus C1
108 VCC =
6.0 V
107 4.5 V
3.0 V
6.0 V
106 4.5 V
3.0 V
105
6.0 V
4.5 V
3.0 V
104
R1 = ∞; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;
VVCOIN = 1/3 VCC FOR VCC = 3.0 V; INH = GND; Tamb = 25°C
R2=3.0 kW
103
R2=100 kW
102 R2=300 kW
101
101
102 103 104 105 106
C1 (pF)
Figure 20. Frequency Offset versus C1
108
107 VCC = 4.5 V; R2 = ∞
106
105
104
103
102
10-7
10-6
10-5 10-4 10-3 10-2 10-1
R1C1
Figure 21. Typical Frequency Lock Range (2fL)
versus R1C1
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11
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