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PDF STLVDS385 Data sheet ( Hoja de datos )
| Número de pieza | STLVDS385 | |
| Descripción | 3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-85MHZ | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STLVDS385
+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT
FLAT PANEL DISPLAY (FPD) LINK-85MHZ
s 20 TO 85 MHz SHIFT CLOCK SUPPORT
s BEST–IN–CLASS SET & HOLD TIMES ON
TxINPUTs
s Tx POWER CONSUMPTION <130 mW (typ)
@85MHz GRAYSCALE
s Tx POWER-DOWN MODE <200µW (max)
s SUPPORTS VGA, SVGA, XGA aND SINGLE/
DUAL PIXEL SXGA.
s NARROW BUS REDUCES CABLE SIZE AND
COST
s UP TO 2.38 Gbps THROUGHPUT
s UP TO 297.5 Megabytes/sec BANDWIDTH
s 345 mV (typ) SWING LVDS DEVICES FOR
LOW EMI
s PLL REQUIRES NO EXTERNAL
COMPONENTS
s COMPATIBLE WITH TIA/EIA -644 LVDS
STANDARD
DESCRIPTION
The STLVDS385 transmitter converts 28 bits of
LVCMOS/LVTTL data into four LVDS (Low
Voltage Differential Signaling) data streams. A
phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS
TSSOP56
link. Every cycle of the transmit clock 28 bits of
input data are sampled and transmitted. At a
transmit clock frequency of 85 MHz, 24 bits of
RGB data and 3 bits of LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitted
at a rate of 595 Mbps per LVDS data channel.
Using a 85 MHz clock, the data throughput is
297.5 Mbytes/sec. The transmitter can be
programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising
edge or Falling edge strobe transmitter will inter
operate with a Falling edge strobe Receiver
without any translation logic.
ORDERING CODES
Type
STLVDS385BTR
Temperature
Range
-10 to 70°C
Package
TSSOP56 (Tape & Reel)
Comments
2000 parts per reel
February 2004
1/14
1 page  
STLVDS385
TRANSMITTER SWITCHING CHARACTERISTICS (VCC = 3.3V, TJ = -10 to 70°C unless otherwise
noted. Typical values are referred to TA = 25°C)
Symbol
Parameter
Test
Conditions
Min.
Typ.
Max.
Unit
tLLHT
tLLLT
tTPP0
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
tTPP0
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
tTPP0
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
tSTC
tHTC
tCCD
LVDS Low-to-High Transition Time (Fig. 4)
LVDS High-to-Low Transition Time (Fig. 4)
Transmitter Output Pulse Position for BIT 0
(Fig.11 - Note 3)
Transmitter Output Pulse Position for BIT 1
Transmitter Output Pulse Position for BIT 2
Transmitter Output Pulse Position for BIT 3
Transmitter Output Pulse Position for BIT 4
Transmitter Output Pulse Position for BIT 5
Transmitter Output Pulse Position for BIT 6
Transmitter Output Pulse Position for BIT 0
(Fig.11 - Note 3)
Transmitter Output Pulse Position for BIT 1
Transmitter Output Pulse Position for BIT 2
Transmitter Output Pulse Position for BIT 3
Transmitter Output Pulse Position for BIT 4
Transmitter Output Pulse Position for BIT 5
Transmitter Output Pulse Position for BIT 6
Transmitter Output Pulse Position for BIT 0
(Fig.11 - Note 3)
Transmitter Output Pulse Position for BIT 1
Transmitter Output Pulse Position for BIT 2
Transmitter Output Pulse Position for BIT 3
Transmitter Output Pulse Position for BIT 4
Transmitter Output Pulse Position for BIT 5
Transmitter Output Pulse Position for BIT 6
TxIN Setup to TxCLK IN (Fig. 6)
TxIN Hold to TxCLK IN (Fig. 6)
TxCLK IN to TxCLK OUT Delay (Fig. 7)
tCCD
tJCC
TxCLK IN to TxCLK OUT Delay (Fig. 7)
Transmitter Jitter Cycle-to-Cycle (Fig. 12 - Note 4)
tPLLS
tPDD
Transmitter Phase Lock Loop Set (Fig. 8)
Transmitter Power Down Delay (Fig. 10)
f = 40 MHz
f = 65 MHz
f = 85 MHz
TA = 25°C,
VCC = 3.3V
f = 85 MHz
f = 65 MHz
f = 40 MHz
-0.25
0.75
0.75
0
1.5
1.5
0.25
3.32
6.89
10.46
14.04
17.61
21.18
-0.20
3.57
7.14
10.71
14.29
17.86
21.43
0
3.82
7.39
10.96
14.54
18.11
21.68
0.20
2.00
4.20
6.39
8.59
10.79
12.99
-0.20
2.20
4.40
6.59
8.79
10.99
13.19
0
2.40
4.60
6.79
8.99
11.19
13.99
0.20
1.48
3.16
4.84
6.52
8.20
9.88
2.5
0
3.8
1.68
3.36
5.04
6.72
8.40
10.08
1.88
3.56
5.24
6.92
8.60
10.28
6.3
2.8 7.1
110 150
210 230
350 370
10
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ms
ns
Note 1: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ∆VOD).
Note 2: VOS previously referred as VCM.
Note 3: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and tempera-
ture range. This parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 4: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter
is measured with a cycle-to-cycle jitter of ± 3ns applied to the input clock signal while data inputs are switching (See Figures 15 and 16). A
jitter event of 3ns, represents worse case jump in the clock edge from most graphics controller VGA chips currently available.
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal
switching needed to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
5/14
5 Page 
Figure 10 : Transmitter Power Down Delay
STLVDS385
Figure 11 : Transmitter LVDS Output Pulse Position Measurement
11/14
11 Page | ||
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