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PDF STLVD111 Data sheet ( Hoja de datos )
| Número de pieza | STLVD111 | |
| Descripción | PROGRAMMABLE LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK DRIVER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STLVD111
PROGRAMMABLE LOW VOLTAGE
1:10 DIFFERENTIAL LVDS CLOCK DRIVER
s 100ps PART-TO PART SKEW
s 50ps BANK SKEW
s DIFFERENTIAL DESIGN
s MEETS LVDS SPEC. FOR DRIVER
OUTPUTS AND RECEIVER INPUTS
s REFERENCE VOLTAGE AVAILABLE
OUTPUT VBB
s LOW VOLTAGE VCC RANGE OF 2.375V TO
2.625V
s HIGH SIGNALLING RATE CAPABILITY
(EXCEEDS 622MHz)
s SUPPORT OPEN, SHORT AND
TERMINATED INPUT FAIL-SAFE (LOW
OUTPUT STATE)
s PROGRAMMABLE DRIVERS POWER OFF
CONTROL
TQFP32
DESCRIPTION
The STLVD111 is a low skew programmable 1 to
10 differential LVDS driver, designed for clock
distribution. The select signal is fanned out to 10
identical differential outputs.
The STLVD111 is provided with a 11 bit shift
register with a serial in and a Control Register.
The purpose is to enable or power off each output
clock channel and to select the clock input. The
STLVD111 is specifically designed, modelled and
produced with low skew as the key goal. Optimal
design and layout serve to minimize gate to gate
skew within a device. The net result is a
dependable guaranteed low skew device.
The STLVD111 can be used for high performance
clock distribution in 2.5V systems with LVDS
levels. Designers can take advantage of the
device’s performance to distribute low skew
clocks across the backplane or the board.
ORDERING CODES
Type
STLVD111BF
STLVD111BFR
Temperature
Range
-40 to 85 °C
-40 to 85 °C
Package
TQFP32 (Tray)
TQFP32 (Tape & Reel)
Comments
250 parts per Tray
2400 parts per reel
December 2002
1/12
1 page  
STLVD111
SPECIFICATION OF CONTROL REGISTER
The STLVD111 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose
is to enable or power of each output clock channel and to select the clock input. The STLVD111 provides
two working modality:
PROGRAMMED MODE (EN=1)
The shift register have a serial input to load the working configuration. Once the configuration is loaded
with 11 clock pulse, another clock pulse load the configuration into the control register. The first bit on the
serial input line enables the outputs Q9 and Q9, the second bit enables the outputs Q8 and Q8 and so on.
The last bit is the clock selection bit. To restart the configuration of the shift register a reset of the state
machine must be done with a clock pulse on CK and the EN set to Low. The control register shift register
can be configured on time after each reset.
STANDARD MODE (EN=0)
In Standard Mode the STLVD111 isn’t programmable, all the clock outputs are enabled. The LVDS clock
input is selected from Clock 0 or Clock 1 with the SI pin as shown in the Truth Table below.
TRUTH TABLE OF STATE MACHINE INPUTS
EN SI CK
OUTPUT
L L X All Output Enabled, Clock 0 selected, Control Register disabled
L H X All Output Enabled, Clock 1 selected, Control Register disabled
HL
First stage stores "L", other stages store the data of previous stage
HH
First stage stores "H", other stages store the data of previous stage
LX
Reset of the state machine, Shift register and Control Register
SERIAL INPUT SEQUENCE
BIT#10
CLK_SEL
BIT#9
Q0
BIT#8
Q1
BIT#7
Q2
BIT#6
Q3
BIT#5
Q4
BIT#4
Q5
BIT#3
Q6
BIT#2
Q7
BIT#1
Q8
BIT#0
Q9
TRUTH TABLE OF THE CONTROL REGISTER
BIT#10
L
H
X
BIT#(0-9)
H
H
L
Qn(0-9)
Clock 0
Clock 1
Qn Output Disabled
TRUTH TABLE
CK EN
LL
LL
LL
LL
LL
LL
All drivers enable
SI
L
L
L
H
H
H
CLK 0
L
H
Open
X
X
X
CLK 0
H
L
Open
X
X
X
CLK 1
X
X
X
L
H
Open
CLK 1
X
X
X
H
L
Open
Q (0-9)
L
H
L
L
H
L
Q(0-9)
H
L
H
H
L
H
5/12
5 Page 
DIM.
A
C
D
N
T
Ao
Bo
Ko
Po
P
STLVD111
Tape & Reel TQFP32 MECHANICAL DATA
MIN.
12.8
20.2
60
9.5
9.5
2.1
3.9
11.9
mm.
TYP
MAX.
330
13.2
22.4
9.7
9.7
2.3
4.1
12.1
MIN.
0.504
0.795
2.362
0.374
0.374
0.083
0.153
0.468
inch
TYP.
MAX.
12.992
0.519
0.882
0.382
0.382
0.091
0.161
0.476
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet STLVD111.PDF ] | |
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