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PDF GP521 Data sheet ( Hoja de datos )
| Número de pieza | GP521 | |
| Descripción | General Purpose Controller / Memory Chip | |
| Fabricantes | Gennum Corporation | |
| Logotipo |  |
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General Purpose
Controller / Memory Chip
for Hearing Instruments
FEATURES
• general purpose
• EEPROM non-volatile memory
• 8 programmable current sink (PCS) control outputs
• can be configured with 6 PCS outputs for hearing
instruments (two switchable, four non-switchable)
• status register
• data transmission error detection
• synchronization of GP521 internal clocks with program
unit clock
STANDARD PACKAGING
• Chip (129 x 112 mils)
Au Bump
DESCRIPTION
The GP521 is a general purpose controller/memory chip in-
tended for use with audio signal path circuits in programmable
hearing instruments.
The GP521 uses a flexible communication standard which
allows room for future growth in programmable functions for
hearing instruments. The communication with the program unit
is over a bi-directional serial data link. Error detection circuitry
is used to avoid undesired changes in programmed settings.
GP521 - DATA SHEET
An information transfer dialogue consists of the address and
data for a register sent to the GP521 and the register contents
returned by the GP521. The function controlled by an output of
the GP521 is defined by the signal path circuit allowing current
controlled parameters. The relationship between the GP521
register addresses and the function on the signal path circuit
is defined by a data file in the programming unit. With this
format, any software developed for the GP521 can be used for
future generations of Gennum’s controller/memory circuits
and audio signal path circuits.
The GP521 uses EEPROM cells as the long term memory
element. These cells will retain the stored data when the power
supply is disconnected. Each EEPROM cell is combined with
a temporary (RAM) memory cell which makes it possible to
evaluate various control settings prior to saving them in the
long term EEPROM memory.
The GP521 controls the audio signal path circuit using eight
Programmable Current Sinks (PCS). Each PCS has 16 pro-
grammable settings. The circuit can be configured for either 6
or 8 PCS outputs. When used with a single pole single throw
switch (SPST) under the 6 PCS configuration , it is possible to
design a hearing instrument with two programmed settings
(i.e. adjusting a low cut filter for either noisy or quiet back-
ground environments). The 8 output configuration may be
used for circuits that require more programmable but non-
switchable settings. An external reference current is used for
the PCS’s so that the PCS outputs can track with the currents
in the audio signal path circuit.
BLOCK DIAGRAM
IO1
10
IO2
9
CONTROL OUTPUTS
CONTROL OUTPUTS
IO3 IO4 IO5 IO6
8 7 15 13
IO7
12
IO8
11
4 BIT
EEPROM
DAC
V
CC 3
GND 5
4 BIT
EEPROM
DAC
4 BIT
EEPROM
DAC
4 BIT
EEPROM
DAC
4 BIT
EEPROM
DAC
4 BIT
EEPROM
DAC
4 BIT
EEPROM
DAC
4 BIT
EEPROM
DAC
REFERENCE
CURRENT
17 I RIR
2
DATA
SERIAL TO PARELLEL
CONVERSION
DATA ERROR CHECKING
CONTROLLER TIMING
EEPROM
VOLTAGE
MULTIPLIER
STATUS &
OPERATION
REGISTER
1
CLOCK
Revision Date: May 1998
4
SW OFF
6
OS1
OSCILLATOR
16
N/C
14
N/C
Document No. 510 - 79 - 06
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996
Web Site: www.gennum.com E-mail: [email protected]
1 page  
PIN DESCRIPTION
CLOCK - The clock pulses for synchronization of the data
transfer. The clock pulses are provided by the programming
unit.
DATA - The input / output pin allow for serial data transfer
between the GP521 and the programming unit.
VCC - Recommended supply voltage for GP521 is 1.3V
SWOFF - The logic state of SWOFF determines whether the
GP521 operates at 6 or 8 PCS configuration. When SWOFF is
high, all eight (IO1 to IO8) PCS are available (8 PCS
configuration) Figure 10.
CLOCK
DATA
VCC
SWOFF
GND
OS1
Io4
Io3
1
2
3
4
5
6
7
8
17 IR
16 NC
15 Io5
14 NC
GP521
13
12
Io6
Io7
11 Io8
10 Io1
9 Io2
Fig.10 EIGHT OUTPUT CONFIGURATION
When SWOFF is low, four PCS (IO5 to IO8) are available;
availablility of other two PCS is dependent on the voltage on
pin OS1. For this configuration (6 PCS configuration) the
necessary hardware connections are presented in Figure 11.
CLOCK
DATA
VCC
SWOFF
GND
OSI
Io4
Io3
1
2
3
4
5
6
7
8
GP521
17
16
15
14
13
12
11
10
9
IR
NC
Io5
NC
Io6
Io7
Io8
Io1
Io2
Fig. 11 SIX OUTPUT CONFIGURATION
OS1 - The voltage level on this pin determines the selection
of four PCS (IO1 to IO4) for 6 PCS configuration. As indicated
on Figure 11, pin IO1, IO2 and IO3, IO4 are connected together.
If OS1 is low, IO1 and IO3 are set to high impedance. Therefore
the PCS, IO2 and IO4 are permitted to sink current.
Similarly if OS1 is high, IO2 and IO4 are set as high impedance
points. This allows PCS IO1 and IO3 to sink current.
TABLE 1 EFFECTS OF SWOFF AND OS1 INPUTS
SWOFF OS1
01
00
1x
1x
1x
1x
xx
xx
xx
xx
OUTPUT
PCS Register Address
( IO1 and IO3)*
( IO2 and IO4)*
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
(0001000 and 0001010)
(0001001 and 0001011)
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001110
Note* The complementary outputs are set as high
impedance points.
IO1 - IO8 - Each pin is the output of the specific Programmable
Current Sink (PCS). Each PCS consists of four bit EEPROM
memory, Digital to Analog Converter (DAC) and current sink.
The EEPROM stores the four bit information written during
initialization of the system. Four bit memory allows for 16
settings of the current sink. For simplicity, consider the
current sink as a variable resistor. The value of this resistor is
dependent on the DAC setting; DAC is controlled by the binary
value of the RAM memory. To define output current of the
current sink, it is necessary to set the voltage applied to the
PCS output. This voltage is recommended to be 0.5 V. If the
binary value of the EEPROM increases by one, the value of the
output current increases by 0.125 x IR.
IR - The reference current delivered from the outside source
(eg. GP520A). This current determines the incremental value
of the programmable current sink for each increase of the
EEPROM address value. The valid addresses run from 0
through to 15. Each step is defined as ∆I = IR x 0.125,
therefore maximum current at setting 15 is equal to I15 = IR x
0.125 x 15.
5 510 - 79 - 06
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet GP521.PDF ] | |
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