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PDF GF9330 Data sheet ( Hoja de datos )
| Número de pieza | GF9330 | |
| Descripción | High Performance HDTV/SDTV Deinterlacer | |
| Fabricantes | Gennum | |
| Logotipo |  |
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Features
• 10/8-bit progressive scan output up to 1080p60
• support for multiplexed and non-mutiplexed Y/C video
• multi-directional edge detection processing
• adaptive inter-field motion detection
• seamless interface to Gennum's GF9331 motion co-
processor
• fully configurable to support custom video modes
• 3:2 film mode operation for HDTV/SDTV inputs
• programmable noise reduction and detail enhancement
• de-interlace, pass-through and film rate down conversion
modes of operation
• seamless interface to popular ADCs and NTSC/PAL
decoders
• ability to extract HVF information from embedded TRS
• selectable rounding and clipping of output data
• selectable blanking of active video lines
• HVF output signals with programmable output video
cropping
• serial/parallel host interface
• 3.3V supply for device I/O and 2.5V for core logic
• 5V tolerant inputs
Applications
• HDTV Up/Down Converters
• Production Equipment
• Video Walls
• Projection Systems
• Plasma Displays
• LCD TVs
• Home Theatre Systems
• HD DVD Players
GF9330 High Performance
HDTV/SDTV Deinterlacer
GF9330 Data Sheet
Device Overview
The GF9330 is a 10-bit high performance VDSP engine that
performs high quality motion adaptive de-interlacing of
interlaced digital video signals. The GF9330 supports
standard definition (SDTV) and high definition (HDTV) signal
formats and clock rates up to 1080p60 with support for
arbitrary display modes.
The GF9330 uses multi-directional adaptive filters for edge
processing, an adaptive vertical motion filter and an adaptive
inter-field motion filter. The GF9330 features detail
enhancement and noise reduction capabilities. The GF9330
also supports 3:2 pull-down, static/freeze-frame detection and
compensation and film rate conversions. The GF9330 may
operate as a stand-alone de-interlacer or may be used with
the GF9331 Motion Co-processor to enable higher quality HD/
SD de-interlacing with edge and vertical motion detection. The
two devices can be configured in tandem such that the
GF9331 sends edge detection and vertical motion filter control
information to the GF9330. These control signals adaptively
switch the GF9330's internal filters on a pixel-by-pixel basis.
The GF9330 integrates all required line delays and
seamlessly interfaces to off chip SDRAMs that form the
required field delays. The device may also operate in by-pass
mode should no processing of the input signal be desired.
Ordering Information
Part Number
GF9330-CBP
Package
328 PIN BGA
Temp. Range
0oC to 70oC
Timing
Generator
Y/C
Input
Processing
Host
Interface
3:2
Pulldown
Detector
Noise
Reducer
Detail
Enhancer
Inter-field
Motion
Detector
Control bus from GF9331
Edge Adaptive
Interpolator
Vertical Motion
Adaptive Interpolator
Inter-field Motion
Adaptive Interpolator
Field Merging
Selector
External Memory Interface
Block Diagram
Output
Processing
Processed Y/C
Proprietary and Confidential 18283 - 4 June 2004
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1 page  
GF9330 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Symbol
HOST_EN
SER_MD
CS
DAT_IO[7:0]
R_W
A_D
VCLK_OUT
Y1_OUT[11:0]
Y2_OUT[11:0]
C1_OUT[11:0]
C2_OUT[11:0]
LOCK_32
XSEQ[3:0]
H_OUT
F_OUT
V_OUT
S1_CLK
S1_CS
Pin Grid
E4
G1
P2
R4, R3, R2, R1, T4, T3,
T2, T1
P3
P1
A20
D18, E20, E19, E18, F20,
F19, F18, F17, G20, G19,
G18, G17
H20, H19, H18, H17, J20,
J19, J18, J17, K20, K19,
K18, L18
L19, L20, M17, M18, M19,
M20, N17, N18, N19, N20,
P17, P18
P19, P20, R17, R18, R19,
R20, T18, T19, T20, U18,
U19, U20
B20
D19, D20, C19, C20
V20
V19
W20
Y10
Y3
Type
Description
I Host interface enable. When set HIGH, the GF9330 will be configured through
the host interface. On a high to low transition of HOST_EN the GF9330 will
replace all register settings in the host interface with the values present on the
external pins of the device including: STD[4:0], MODE[2:0], FVH_EN, FF_EN
and XVOCLK_SL.
I Host interface mode selection. Enables serial mode operation when HIGH.
Enables parallel mode operation when LOW.
I Functions as an active low chip select input for host interface parallel mode
operation. Functions as a serial clock input for host interface serial mode
operation.
I/O Host interface bi-directional data bus for parallel mode. In serial mode, DAT[7]
serves as the serial data output pin and DAT[0] serves as the serial data input
pin.
I Host interface Read/Write control for parallel mode. A read cycle is defined
when HIGH, a write cycle is defined when LOW.
I Host interface Address/Data control for parallel mode. The data bus contains
an address when HIGH, a data word when LOW. In serial mode, this pin
serves as the chip select (active low).
O Video output clock. Output frequency based on selected output standard. See
3.9 Modes of Operation.
O Output data bus for separate luminance or multiplexed luminance and colour
difference video data. See 3.10.2 12-bits Output Resolution.
O Output data bus for luminance video data during dual pixel mode operation.
See 3.10.2 12-bits Output Resolution.
O Output data bus for colour difference video data.
See 3.10.2 12-bits Output Resolution.
O Output data bus for colour difference video data during dual pixel mode
operation. See 3.10.2 12-bits Output Resolution.
O Control signal output. When the GF9330’s internal algorithm detects a 3:2
sequence in the video stream the LOCK_32 signal is set HIGH. Otherwise,
LOCK_32 is LOW.
I/O Control signal input/output. For external 3:2 sequence detection, the
XSEQ[3:0] pins will be used to provide the 3:2 sequence information. For
internal 3:2 detection the XSEQ[3:0] pins output the detected 3:2 sequence
information. See Figure 3-12: Sequence Detection Input Signals.
O Output control signal. H_OUT is HIGH during horizontal blanking.
O Output control signal. F_OUT is LOW during field 1 and HIGH during field 2.
O Output control signal. V_OUT is HIGH during vertical blanking.
O SDRAM bank 1 clock.
O Active low SDRAM chip select for Field Buffer 1.
Proprietary and Confidential 18283 - 4 June 2004
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5 Page 
GF9330 Data Sheet
Table 2-5: AC Electrical Characteristics - Host Interfaces (Continued)
The Host Interface signals include HOST_EN, SER_MD, CS, DAT_IO[7:0], R_W and A_D.
VDDIO = 3.0 to 3.6V, VDDCORE = 2.25 to 2.75V, TA = 0 to 70oC, unless otherwise shown.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Output Data Hold Time
VDDIO=3.6V,
CL=15pF load
tOH_HI
2.0
-
- ns
Output Enable Time
VDDIO=3.6V,
CL=15pF load
tOEN_HI
-
- 15 ns
Output Disable Time
VDDIO=3.6V,
CL=15pF load
tODIS_HI
-
- 15 ns
Output Data Rise/Fall Time
VDDIO=3.6V,
CL=15pF load
tODRF_HI
-
- 2.0 ns
a.Based on simulation results, verified during device characterization process.
b.50% levels.
c.20% to 80% levels.
Notes
a
a
a
a, c
Proprietary and Confidential 18283 - 4 June 2004
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GF9330.PDF ] | |
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