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PDF UPD44323362 Data sheet ( Hoja de datos )
| Número de pieza | UPD44323362 | |
| Descripción | 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44323362
32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
1M-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The µPD44323362 is a 1,048,576 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The µPD44323362 is suitable for applications which require high-speed, low voltage, high-density memory and wide
bit configuration, such as cache and buffer memory.
The µPD44323362 is packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
• Fully synchronous operation
• HSTL Input / Output levels
• Fast clock access time: 2.0 ns / 250 MHz
• Asynchronous output enable control: /G
• Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)
• Common I/O using three-state outputs
• Internally self-timed write cycle
• Late write with 1 dead cycle between Read-Write
• User-configurable outputs: Controlled impedance outputs or push-pull outputs
• Boundary scan (JTAG) IEEE 1149.1 compatible
• 2.5 ± 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply
• 119 bump BGA package, 1.27 mm pitch, 14 mm × 22 mm
• Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number
µPD44323362F1-C40-FJ1
Access time
2.0 ns
Clock frequency
250 MHz
Package
119-pin PLASTIC BGA
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16379EJ4V0DS00 (4th edition)
Date Published May 2004 NS CP(K)
Printed in Japan
The mark Ì shows major revised points.
2002
1 page  
µPD44323362
Programmable Impedance / Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to
adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by
the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175
ohm and 350 ohm. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly
affected by drifts in supply voltage and temperature. The impedance update of the output driver occurs only when the
SRAM is in high impedance. Write and Deselect operations will synchronously switch the SRAM into and out of high
impedance, therefore, triggering an update. Power up requirements for the SRAM are that VDD must be powered
before or simultaneously with VDDQ followed by VREF; inputs should be powered last. The limitation on VDDQ is that it
must not exceed VDD during power up. In order to guarantee the optimum internally regulated supply voltage, the
SRAM requires 4096 clock cycles of power-up time after VDD reaches its operating range. And CID impedance is not
updated during the clock stopped.
Sleep Mode
Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep Mode, the output
will go to a high impedance state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (tZZR) is required before the SRAM resumes normal operation. And CID impedance is not updated
during the sleep mode.
Data Sheet M16379EJ4V0DS
5
5 Page 
Read Operation
/K
K
Address
/SS
/SW
/G
DQ
tKHAX
tAVKH
tKHKH
tKHKL
tKLKH
abcde f gh i
tKHSX
tSVKH
tKHWX
tWVKH
tGHGL
jk
tGHQZ
tGLQX
tGLQV
tKHQZ2
tKHQX2
High-Z
High-Z
Qa Qb Qc
Qe Qf Qg
Qi
tKHQX
tKHQV
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet UPD44323362.PDF ] | |
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