PDF UPD44321182 Data sheet ( Hoja de datos )

Número de pieza	UPD44321182
Descripción	(UPD44321182 / UPD44321362) 32M-BIT ZEROSB SRAM PIPELINED OPERATIO
Fabricantes	NEC
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No Preview Available ! www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT µ PD44321182, 44321362 32M-BIT ZEROSBTM SRAM PIPELINED OPERATION Description The µPD44321182 is a 2,097,152-word by 18-bit and the µPD44321362 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44321182 and µPD44321362 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD44321182 and µPD44321362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD44321182 and µPD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • Low voltage core supply : VDD = 3.3 ± 0.165 V / 2.5 ± 0.125 V • Synchronous operation • 100 percent bus utilization • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for pipelined operation • All registers triggered off positive clock edge • 3.3V or 2.5V LVTTL Compatible : All inputs and outputs • Fast clock access time : 3.2 ns (200 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4 (µPD44321362) /BW1 and /BW2 (µPD44321182) • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. Document No. M16024EJ5V0DS00 (5th edition) Date Published April 2005 NS CP(K) Printed in Japan The mark shows major revised points. 2002, 2005 1 page µPD44321182, 44321362 100-pin PLASTIC LQFP (14 × 20) [µPD44321362GF] Marking Side I/OP3 I/O17 I/O18 VDDQ VSSQ I/O19 I/O20 I/O21 I/O22 VSSQ VDDQ I/O23 I/O24 VDD VDD VDD VSS I/O25 I/O26 VDDQ VSSQ I/O27 I/O28 I/O29 I/O30 VSSQ VDDQ I/O31 I/O32 I/OP4 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/OP2 I/O16 I/O15 VDDQ VSSQ I/O14 I/O13 I/O12 I/O11 VSSQ VDDQ I/O10 I/O9 VSS VDD VDD ZZ I/O8 I/O7 VDDQ VSSQ I/O6 I/O5 I/O4 I/O3 VSSQ VDDQ I/O2 I/O1 I/OP1 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M16024EJ5V0DS 5 5 Page Partial Truth Table for Write Enables [µPD44321182] Operation Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / All Bytes Write Abort / NOP Remark × : don’t care /WE H L L L L [µPD44321362] Operation Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / Byte 3 (I/O [17:24], I/OP3) Write Cycle / Byte 4 (I/O [25:32], I/OP4) Write Cycle / All Bytes Write Abort / NOP Remark × : don’t care /WE H L L L L L L ZZ (Sleep) Truth Table ZZ ≤ 0.2 V Open ≥ VDD − 0.2 V Chip Status Active Active Sleep µPD44321182, 44321362 /BW1 × L H L H /BW2 × H L L H /BW1 × L H H H L H /BW2 × H L H H L H /BW3 × H H L H L H /BW4 × H H H L L H Data Sheet M16024EJ5V0DS 11 11 Page

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