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PDF ADV212 Data sheet ( Hoja de datos )
| Número de pieza | ADV212 | |
| Descripción | Wavescale Video Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Implementation of a JPEG2000-compatible video CODEC for
video and still images through the ADV212 Wavescale
video compression/decompression engine
Identical pinout and footprint to the ADV202; and support
for all the functionality of the ADV202
Power reduction of at least 30% compared with ADV202
JTAG/boundary scan support
Patented spatial ultraefficient recursive filtering (SURF)
technology for low power, low cost wavelet-based
compression
Support for both 9/7 and 5/3 wavelet transforms with up to
5 levels of transform
9/7 wavelet support for tiles up to 1.048 million samples
5/3 wavelet support for tiles up to 262,144 samples
Video interface direct support for ITU-R BT.656, SMPTE 125M
PAL/NTSC, SMPTE 274M, SMPTE 293M (525p), and ITU-R
BT.1358 (625p) or any video format with a maximum input
rate of 65 MSPS for irreversible mode or 40 MSPS for
reversible mode
Programmable tile/image size with widths of up to
4096 pixels in single-component mode; maximum
tile/image height of 4096 pixels
Ability to combine 2 or more ADV212s to support full-frame
SMPTE 274M HDTV (1080i) or SMPTE 296M (720p)
Flexible, asynchronous SRAM-style host interface support
for glueless connection to most 16-/32-bit microcontrollers
and ASICs
2.5 V or 3.3 V input/output and 1.5 V core supply
2 package and speed grade options
12 mm × 12 mm, 121-ball CSP_BGA with a speed grade of
115 MHz
13 mm × 13 mm, 144-ball CSP_BGA with a speed grade of
150 MHz
Wavescale Video Codec
ADV212
APPLICATIONS
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders
GENERAL DESCRIPTION
The ADV212 Wavescale® video compression/decompression
(CODEC) is a single-chip JPEG2000 CODEC targeted for video
and high bandwidth image compression applications that can
benefit from the enhanced quality and features provided by the
JPEG2000 (J2K) ISO/IEC15444-1 image compression standard.
The part implements the computationally intensive operations
of the JPEG2000 image compression standard and provides
fully compliant code stream generation for most applications.
The dedicated video port of the ADV212 provides glueless con-
nection to common digital video standards such as ITU-R
BT.656, SMPTE 125M, SMPTE 293M (525p), ITU-R BT.1358
(625p), SMPTE 274M (1080i), and SMPTE 296M (720p). A
variety of other high speed, synchronous pixel and video
formats can also be supported by using the programmable
framing and validation signals.
The ADV212 is an upgrade version of the ADV202, which is
identical in pinout and footprint. It supports all of the func-
tionality of the ADV202 and has the following additional
options: JTAG/boundary scan support and power reduction of
at least 30% compared with the ADV202.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved.
1 page  
CLOCK AND RESET SPECIFICATIONS
Table 3.
Parameter
MCLK Period
MCLK Frequency
MCLK Width Low
MCLK Width High
VCLK Period
VCLK Frequency
VCLK Width Low
VCLK Width High
RESET Width Low
Mnemonic
tMCLK
fMCLK
tMCLKL
tMCLKH
tVCLK
fVCLK
tVCLKL
tVCLKH
tRESET
1 For a definition of MCLK, see Figure 32.
Min Typ
13.3
10
6
6
13.4
20
5
5
5
MCLK
VCLK
tMCLKL
tMCLK
tMCLKH
tVCLKL
tVCLK
tVCLKH
Figure 2. Input Clock
Max
100
75.18
50
74.60
ADV212
Unit
ns
MHz
ns
ns
ns
MHz
ns
ns
MCLK cycles1
Rev. B | Page 5 of 44
5 Page 
DREQ
DACK
RDFB
HDATA
DREQPULSE
tDREQ
DACKHIGH
DACKLOW
tRDSU
tRD tHD
01
Figure 11. Single Read Cycle for Fly-By DMA Mode
(DREQ Pulse Width Is Programmable)
2
tRDHD
FCS0
RD
FSRQ0
FIFO NOT EMPTY
tRD
HDATA
RDFSRQ
FIFO EMPTY
tHD
01
Figure 12. Single Read Access for DCS DMA Mode
ADV212
Rev. B | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADV212.PDF ] | |
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