PDF NCV7510 Data sheet ( Hoja de datos )

Número de pieza	NCV7510
Descripción	FlexMOS Programmable Peak and Hold PWM MOSFET Predriver
Fabricantes	ON Semiconductor
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No Preview Available ! www.DataSheet4U.com NCV7510 FlexMOSt Programmable Peak and Hold PWM MOSFET Predriver The NCV7510 high side MOSFET predriver is a fully programmable automotive grade product for driving solenoids or other unipolar actuators. The product is optimized for common−rail diesel fuel injection applications and includes an additional synchronous clamp MOSFET predriver. Peak and hold currents, peak dwell time and other features are programmable via the device’s SPI port. Load current is continuously sampled and compared to the programmable 7−bit peak/hold DAC values while the load self−modulates to maintain the desired currents at each of the peak and hold points. Passive fault diagnostics monitor and protect the MOSFETs when a fault is detected. Fault data is available via SPI and an open−drain FAULT output provides immediate fault notification to a host controller. The FlexMOS family of products offers application scalability through choice of external MOSFETs. Features • 4 MHz 16−Bit SPI Communication • 3.3 / 5.0 V Compatible Inputs • Bootstrap for High Side MOSFET • Synchronous Clamp Drive • Cross Conduction Suppression • Self−Protection − Overcurrent and Overvoltage − Antisaturation • Fault Diagnostics − Short to Battery/GND − Open Circuit / Shorted Load − Overvoltage • Open−Drain FAULT Output • Programmable − Peak / Hold Current PWM Thresholds − Overcurrent and Overvoltage − Antisaturation Thresholds − Peak Dwell Time • NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes Benefits • Scalable by Choice of MOSFETs • Reduced Load Power Consumption • Low Host Controller Overhead • Low Standby Current http://onsemi.com 20 1 SO−20L DW SUFFIX CASE 751D MARKING DIAGRAM 20 NCV7510 AWLYYWW 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week PIN CONNECTIONS ENA CONTROL PCLK CSB SCLK SI SO LOOP FAULT OCP 1 20 VB DRN GATE SRC CLAMP PGND SNS+ SNS− DGND VDD ORDERING INFORMATION Device Package Shipping† NCV7510DW SO−20L 37 Units/Rail NCV7510DWR2 SO−20L 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 January, 2005 − Rev. 0 1 Publication Order Number NCV7510/D 1 page NCV7510 Pin Function Descriptions ENA: CMOS input with hysteresis logically ANDed with the CONTROL input to command the predriver outputs. This input has an active pulldown current source. CONTROL: CMOS input with hysteresis logically ANDed with the ENA input to command the predriver outputs. This input has an active pulldown current source. PCLK: Buffered CMOS input with hysteresis. This input controls which DAC register pair is selected for load current comparison. The input is programmed via Auxiliary register ($01) bit D3 to respond to a clock signal (AUX D3=0 default at POR) or a logic level (AUX D3=1.) The pin presents a 12 pF maximum load to the controller. CSB: CMOS input with hysteresis. This input is the active−low chip select input that enables serial data transfer between the host controller and the device. This input has an active pullup current source. SCLK: Buffered CMOS input with hysteresis. This input is the synchronizing clock input for serial data transfer between the micro controller and the device. The pin presents a 12 pF maximum load to the controller. SI: Buffered CMOS input with hysteresis. This pin is the data input to the device’s SPI shift register. Serial data received at this input is transferred from the host controller to the shift register under the control of the CSB and SCLK inputs. The pin presents a 12 pF maximum load to the controller. This input has an active pulldown current source. SO: The CMOS compatible line driver at this pin is the data output from the device’s SPI shift register. Serial data transmitted at this output is transferred from the shift register to the host controller under the control of the CSB and SCLK inputs. The pin is capable of driving 200 pF at 4 MHz and is HI−Z when the CSB input is high. LOOP: The CMOS compatible driver at this pin reflects the state of the control loop. A logic low indicates that load current is less than the programmed DAC reference. FAULT: An open−drain low voltage NMOS output at this pin provides immediate fault indication to a connected host controller. An external resistor is normally connected between this pin and VDD. DGND: Device substrate voltage and VDD return path for mixed signal functions. This pin is the circuit common reference point. OCP: This analog comparator input supplies a reference voltage to the device’s overcurrent fault detection. When the voltage at this pin is less than 4.5 V, the applied voltage is the overcurrent reference voltage. When the voltage is greater than 4.5 V, an internal 3.0 V overcurrent reference is used. The voltage at this pin must not exceed VDD. Applying approximately VDD + 1.4 V will place the NCV7510 in test mode and suspend normal operation. The user is advised to avoid activating the test mode. VDD: +5.0 Vpower supply input. The voltage at this pin initiates power−on reset, supplies power to internal mixed−signal functions and supplies gate charge to the external CLAMP MOSFET. A low ESR external bulk capacitor connected between VDD and PGND is recommended to supply transient gate charge. Several internal reference voltages are derived from VDD. SNS−: The inverting input to the analog current sense amplifier. This input should be Kelvin connected directly to the external current sense resistor’s negative terminal. SNS+: The noninverting input to the analog current sense amplifier. This input should be Kelvin connected directly to the external current sense resistor’s positive terminal. PGND: Return path for the GATE and CLAMP predriver transient currents and the lower input to the CLAMP antisaturation detection comparator. This pin should be star−connected to the CLAMP MOSFET’s source and the external VDD bulk charge capacitor’s negative terminal. CLAMP: External CLAMP MOSFET predrive output. This output switches the CLAMP MOSFET’s gate between VDD and PGND. SRC: Lower input to the GATE antisaturation detection comparator and upper input to the CLAMP antisaturation detector. GATE: External HS MOSFET predrive output. This output switches the HS MOSFET’s gate between VB and PGND. DRN: Upper input to the GATE antisaturation detection comparator, overvoltage detection input, and powerup interlock input. This pin should be connected directly to the HS MOSFET’s drain terminal. VB: Bootstrap or boost input voltage. This input supplies gate charge to the external HS MOSFET. http://onsemi.com 5 5 Page CSB SETUP NCV7510 TRANSFER DELAY CSB SCLK SI SO SI SETUP 1 CSB HOLD 16 SI HOLD MSB IN BITS 14...1 LSB IN MSB OUT SO DELAY BITS 14...1 LSB OUT SO RISE,FALL SEE NOTE Note: Not defined but usually MSB of data just received. Figure 9. SPI Timing 90% VDD 10% VDD http://onsemi.com 11 11 Page

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