STE101P Datasheet PDF - ST Microelectronics
Part Number | STE101P | |
Description | 10/100 Fast Ethernet 3.3V Transceiver | |
Manufacturers | ST Microelectronics | |
Logo | ||
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STE101P
10/100 Fast ethernet 3.3 V transceiver
Features
■ IEEE802.3u 100Base-TX and IEEE802.3 and
10Base-T transceiver
■ Support for IEEE802.3x flow control
■ MII /RMII / SMII interface
■ Auto MDIX supported
■ Provides Full-duplex operation on both
100Mbps and 10Mbps modes
■ Provides MLT-3 transceiver with DC
restoration for Base-line wander compensation
■ Provides loop-back modes for diagnostics
■ Supports external transformer with turn ratio
1.414:1 on Tx/Rx side.
■ Five LED display for operating mode and
functionality signalling
■ Operation from single 3.3V supply
■ High Cable ESD tolerance
■ Standard 64-pin QFP package pinout
■ Industrial temperature compliant
■ Self termination transceiver for external
components and power saving
■ Power dissipation < 200mW
Applications
■ Switches/routers/hubs
■ NIC adapters
■ Game consoles
■ VoIP gateways/phones
■ Network printers
■ DTVs/DVD-Rs
TQFP64 10 x 10
Description
The STE101P is a high performance Fast
Ethernet physical layer interface for 10Base-T and
100Base-TX application.
It was designed with advanced CMOS technology
to provide MII, RMII and SMII interfaces for easy
attachment to 10/100 Media Access Controllers
100Base-TX of IEEE802.3u and 10Base-T of
IEEE802.3
The STE101P supports both half-duplex and full-
duplex operation at 10 and 100 Mbps operation.
Its operating mode can be set using auto
negotiation, parallel detection or manual control. It
also allows for the support of auto-negotiation
functions for speed and duplex detection. The
Automatic MDI / MDIX feature compensates for
using a cross over cable. With Auto MDIX, the
STE101P automatically detects what is on the
other end of the network cable and switches the
TX & RX pins accordingly.
September 2006
DataSheet4 U .com
Rev 1
1/53
www.st.com
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STE101P
List of figures
List of figures
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System diagram of the STE101P application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LED connection for Logic level 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LED connection for Logic level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Transmit isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Normal link pulse timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Fast link pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MII management clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
RMII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SMII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TQFP 64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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