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PDF SA-1110 Data sheet ( Hoja de datos )
| Número de pieza | SA-1110 | |
| Descripción | Intel-R StrongARM SA-1110 Microprocessor | |
| Fabricantes | Intel Corporation | |
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Intel® StrongARM* SA-1110
Microprocessor
Product Features
Brief Datasheet
The Intel®StrongARM SA-1110 Microprocessor (SA-1110) is a device
optimized for meeting portable and embedded application requirements.
The SA-1110 incorporates a 32-bit StrongARM RISC processor capable of
running at up to 206 MHz. The SA-1110 has a large instruction and data
cache, memory-management unit (MMU), and read/write buffers. The
SA-1110 memory bus interfaces to many device types including
synchronous DRAM (SDRAM), synchronous mask ROM (SMROM), and
SRAM-like variable latency I/O devices with a shared data ready signal. In
addition, the SA-1110 provides system support logic, multiple serial
communication channels, a color/gray scale LCD controller, PCMCIA
support for up to two sockets, and general-purpose I/O ports.
s High performance
s Memory bus
— 150 Dhrystone 2.1 MIPS @ 133 MHz
— 235 Dhrystone 2.1 MIPS @ 206 MHz
— Interfaces to ROM, synchronous mask
ROM (SMROM), Flash, SRAM,
SRAM-like variable latency I/O,
DRAM, and synchronous DRAM
(SDRAM)
s Low power (normal mode) †
— Supports two PCMCIA sockets
s 32-way set-associative caches
— <240 mW @1.55 V/1D33atMaSHhzeet4U.com — 16 Kbyte instruction cache
— <400 mW @1.75 V/206 MHz
— 8 Kbyte write-back data cache
s Integrated clock generation
s 32-entry MMUs
— Internal phase-locked loop (PLL)
— Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
— 3.686-MHz oscillator
— 32.768-kHz oscillator
s Power-management features
s Write buffer
— Normal (full-on) mode
— 8-entry, between 1 and 16 bytes each
— Idle (power-down) mode
— Sleep (power-down) mode
s Big and little endian operating modes s Read buffer
— 4-entry, 1, 4, or 8 words
s 3.3-V I/O interface
s 256 mini-ball grid array (mBGA)
† Power dissipation, particularly in idle mode, is strongly dependent on the details of the
system design
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Order Number: 278241-005
April 2000
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SA-1110
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required, the palette RAM may be bypassed and frame buffer data passes directly to the dither
logic. If 16-bit data is required, both the palette RAM and the dither logic are bypassed, and data is
sent directly to the LCD controller pins. The LCD controller supports both TFT and STN panels.
Serial port 0 on the SA-1110 implements the universal serial bus (USB) slave protocol, supporting
three endpoints operating at 12 Mbps, half duplex.
Serial port 1 on the SA-1110 implements universal asynchronous receiver-transmitter (UART) at a
baud rate up to 230 Kbps.
Serial port 2 on the SA-1110 provides logic to support infrared data (IrDA) at either 115 Kbps or 4
Mbps. The low-speed IrDA utilizes the HP-SIR* standard, and the high-speed IrDA implements
the 4 PPM standard.
Serial port 3 on the SA-1110 is a UART channel operating from 56.24 bps to 230 Kbps. Modem
control signals may be implemented via the GPIO pins if required, but for maximum flexibility
these signals are not predefined.
Serial port 4 on the SA-1110 also implements a multimedia communications port or synchronous
serial port (MCP/SSP). These ports are traditionally used for interfacing to specific digital/analog
I/O devices such as codecs, keyboards, touchpads, audio and record/playback. If required, the
SA-1110 provides the user with an option to support both the MCP as well as SSP by dedicating
two GPIO pins to the SSP.
The MCP gluelessly interfaces to the Phillips UCB1200*, which provides support for both audio
and telecom codecs as well as a touchpad interface and 10 general-purpose I/O pins. The SA-1110
contains two pairs of transmit and receive FIFOs to support the telecom and audio data. The
SA-1110 also provides
SSP logic interfaces to
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Texas Instruments* synchronous serial protocols, as well as a subset of the Motorola SPI*
protocol. All of these protocols provide methods to interface to keyboard drivers, serial EPROMs,
ADC/DAC, as well as special-purpose devices such as voice record/playback. The SSP functions
as a master only, communicating to off-chip devices by driving a serial bit-rate clock ranging from
7.2 kHz to 1.8432 MHz, and supports data formats from 4 to 16 bits in length.
Intel® StrongARM SA-1110 Test and Debug Support
The SA-1110 provides debug support via instruction and data breakpoints. These are user-
programmable and are implemented through the coprocessor instructions. In the case of an
instruction breakpoint, the user may halt the processor after execution of an instruction at a specific
address. The data breakpoint allows a user to halt on a specific data pattern as well as on the
reference address to that data pattern. There is a data breakpoint mask register that provides further
qualification on specific data.
The SA-1110 also provides a JTAG interface, which has been specifically targeted to provide
continuity checking for system designs. Supported instructions include EXTEST,
SAMPLE/PRELOAD, CLAMP, BYPASS, HIGH-Z, and IDCODE.
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