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PDF HD6472393 Data sheet ( Hoja de datos )
| Número de pieza | HD6472393 | |
| Descripción | (HD6472355 Series) Series of Microcomputers Built Around The H8s/2000 Cpu | |
| Fabricantes | Renesas | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
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Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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Preface
The H8S/2355 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT™*) and mask ROM
versions are available, providing a quick and flexible response to conditions from ramp-up through
full-scale volume production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer
(WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
www.DataSheet4U.comUse of the H8S/2355 Series enables compact, high-performance systems to be implemented easily.
This manual describes the hardware of the H8S/2355 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Note: * ZTAT is a trademark of Hitachi, Ltd. There is no PROM version of the H8S/2393.
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5.1.1 Features ................................................................................................................. 95
5.1.2 Block Diagram...................................................................................................... 96
5.1.3 Pin Configuration.................................................................................................. 97
5.1.4 Register Configuration.......................................................................................... 97
5.2 Register Descriptions ......................................................................................................... 98
5.2.1 System Control Register (SYSCR)....................................................................... 98
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 99
5.2.3 IRQ Enable Register (IER) ................................................................................... 100
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 101
5.2.5 IRQ Status Register (ISR) .................................................................................... 102
5.3 Interrupt Sources................................................................................................................ 103
5.3.1 External Interrupts ................................................................................................ 103
5.3.2 Internal Interrupts.................................................................................................. 104
5.3.3 Interrupt Exception Handling Vector Table ......................................................... 104
5.4 Interrupt Operation............................................................................................................. 108
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 108
5.4.2 Interrupt Control Mode 0...................................................................................... 111
5.4.3 Interrupt Control Mode 2...................................................................................... 113
5.4.4 Interrupt Exception Handling Sequence ............................................................... 115
5.4.5 Interrupt Response Times ..................................................................................... 117
5.5 Usage Notes ....................................................................................................................... 118
5.5.1 Contention between Interrupt Generation and Disabling ..................................... 118
www.DataSheet4U.com5.5.2 Instructions that Disable Interrupts....................................................................... 119
5.5.3 Times when Interrupts are Disabled ..................................................................... 119
5.5.4 Interrupts during Execution of EEPMOV Instruction .......................................... 119
5.6 DTC Activation by Interrupt.............................................................................................. 120
5.6.1 Overview............................................................................................................... 120
5.6.2 Block Diagram...................................................................................................... 120
5.6.3 Operation .............................................................................................................. 121
Section 6 Bus Controller.................................................................................................. 123
6.1 Overview............................................................................................................................ 123
6.1.1 Features ................................................................................................................. 123
6.1.2 Block Diagram...................................................................................................... 124
6.1.3 Pin Configuration.................................................................................................. 125
6.1.4 Register Configuration.......................................................................................... 125
6.2 Register Descriptions ......................................................................................................... 126
6.2.1 Bus Width Control Register (ABWCR) ............................................................... 126
6.2.2 Access State Control Register (ASTCR).............................................................. 127
6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 128
6.2.4 Bus Control Register H (BCRH) .......................................................................... 131
6.2.5 Bus Control Register L (BCRL) ........................................................................... 133
6.3 Overview of Bus Control ................................................................................................... 134
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6472393.PDF ] | |
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