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Número de pieza | UM6164 | |
Descripción | 8K x 8 High Speed CMOS SRAM | |
Fabricantes | UMC | |
Logotipo | ||
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UM6164
=====~=~== BK x 8 High Speed CMOS SRAM
Features
• High-speed - 45/55/70ns (Max.)
• Low p'ower dissipation
300mW (Typ.) Operating
100J.l.W (Typ.) standby
• Single 5V power supply
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three state outputs
• Data retention supply voltage: 2.0-5,5V
General Description
The UM6164 is a 65,536-bit static random access memory
organized as 8192 words by 8 bits' and operates from a
single 5 volt supply. It is built with UMC's high perform-
ance twin tub CMOS process. Inputs and three-state
outputs are TTL compatible and allow for direct interfacing
with common system bus structures. The UM6164 is
moulded in a standard 28-pin, 600 mil-DIP.
Pin Configuration .
Block Diagram
--<> Vcc
~GND
ROW
DECODE
256 x 256
MEMORY ARRAY
AU
INPUT
DATA
CIRCUIT
COLUMN I/O
.COLUMN DECODER
CS2
CSt
OE
WE
2-43
1 page READ CYCLE 4(1)
ADDRESS
OE
UM6164
1.---------tACS1 -----+--~
t------- tc LZ 1 5 ----~~
1 4 - - - - - t A C S2
t------- tCLZ2 5
DOUT --------------------------~
Notes: 1. WE is high for READ cycle.
2. Device is continuously selected CSl = VI Land CS 2 = VIH.
3. Address valid prior to or coincident with CSl transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state. This parameter is sampled and not 100% tested.
6. CS2 is high.
7. CSl is low.
WRITE CYCLE 1(1)
ADDRESS
twc
OE
WE
DOUT ~~~~~+-+-~~--------------------r---~---------
DIN ----------------------------~~+I~------------.>t><><><~~---
2-47
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet UM6164.PDF ] |
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