UAA3559UN Datasheet PDF - NXP Semiconductors
| Part Number | UAA3559UN | |
| Description | Bluetooth RF Transceiver | |
| Manufacturers | NXP Semiconductors | |
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( DataSheet : www.DataSheet4U.com )
INTEGRATED CIRCUITS
DATA SHEET
UAA3559UH
Bluetooth RF transceiver
Objective specification
2003 Jul 04
www.DataSheet4U.com
www.DataSheet4U.com
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Philips Semiconductors
Bluetooth RF transceiver
Objective specification
UAA3559UH
FUNCTIONAL DESCRIPTION
Transmit chain
VCO; BUFFER AND DIVIDER
The VCO has a fully integrated tank circuit with on-chip
inductors, and an on-chip regulator which minimizes any
frequency disturbances caused by VCC variations. The
VCO regulator requires a decoupling capacitor to be
connected to pad VREG. The VCO operates at twice the
Bluetooth frequency.
The VCO signal is buffered and fed into a divide-by-two
circuit to produce the required Local Oscillator (LO)
frequencies for either transmit (TX) mode or receive
(RX) mode. The large difference between the transmitter
and VCO frequencies reduces transmitter to oscillator
coupling problems.
The output of the divide-by-two circuit drives the main
divider prescaler in the synthesizer and also drives the
TX preamplifier in TX mode, or the RX LO buffer in
RX mode. The high isolation between the VCO buffer and
the main divider ensures that only very small frequency
changes occur when the TX preamplifier or the RX section
are turned on. In the TX mode, the VCO is directly
modulated with GFSK data at pad VMOD.
TRANSMIT PREAMPLIFIER
The TX preamplifier gain is programmable in seven steps
of up to 4 dB. It can either amplify the RF signal up to a
level of 9 dBm (typical), or attenuate the RF signal
to −7.5 dBm (typical), see Table 5.
The output of the TX preamplifier at pads TXA and TXB
can directly drive an antenna via a PIN diode switch and
band filter for Bluetooth power class 2 and 3 applications.
The type of TX preamplifier load can affect the frequency
of the VCO when the preamplifier powers up. This ‘pulling’
effect can be counteracted by changing the time at which
the preamplifier powers up, and is implemented by
selecting one of two possible ramp-up modes: ramp-up
mode 0 or ramp-up mode 1. In ramp-up mode 0, the
preamplifier powers up on the rising edge of STCTR.
In ramp-up mode 1, the preamplifier powers up on the
falling edge of STCTR; see Table 3 and timing
diagrams Figs 2 and 3.
The divider ratio is programmable to any value in the range
2304 to 2559 inclusive; see Table 6.
REFERENCE DIVIDER
The reference divider is clocked by the reference signal at
either 12 or 13 MHz via pad REFCLK. The divider ratio is
programmable to 12 or 13. The circuit operates in the
range 150 to 500 mV (RMS); see Table 4.
PHASE COMPARATOR
The outputs of both the main divider and reference divider
drive a phase comparator. Its charge-pump circuit outputs
current pulses at pad CP. The CP signal connects to
pad VTUNE to complete the PLL, which controls and
phase locks the VCO frequency. The duration of a current
pulse is equal to the difference in time between the arrival
of the leading edges of both dividers outputs. If the leading
edge from the main divider arrives first, the charge-pump
sinks current. If the leading edge from the reference divider
arrives first, the charge-pump sources current. The
CP signal current can be integrated by connecting an
external RC loop filter to pad VTUNE as shown in Fig.5.
An internal drift compensation circuit maintains the VCO
frequency when the synthesizer is deactivated during
open loop modulation. It requires an external capacitor to
be connected to pad DRIFTCOMP.
Additional internal circuits ensure that the gain of the
phase comparator remains linear even for small phase
errors.
Serial programming bus
The IC is programmed by a simple 3-line unidirectional
serial bus comprising data (S_DATA), clock (S_CLK) and
enable (S_EN). The serial data is loaded as a burst that is
framed by S_EN. The programming clock edges and
corresponding data bits are ignored until S_EN
goes LOW. The program data is read directly by the main
divider when S_EN goes HIGH. Signals S_DATA and
S_EN should change value on the falling edge of S_CLK.
When inactive, S_CLK should be held LOW.
Synthesizer
MAIN DIVIDER
The main divider is clocked by the RF signal from the VCO
via the divide-by-two circuit at a frequency in the range
2402 to 2481 MHz.
2003 Jul 04
5
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| Information | Total 22 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ UAA3559UN.PDF Datasheet ] | |
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