GVT7C1359A Datasheet PDF - Cypress Semiconductor
| Part Number | GVT7C1359A | |
| Description | (GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAM | |
| Manufacturers | Cypress Semiconductor | |
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( DataSheet : www.DataSheet4U.com )
327
CY7C1359A/GVT71256T18
256K x 18 Synchronous-Pipelined Cache Tag RAM
Features
• Fast match times: 3.5, 3.8, 4.0 and 4.5 ns
• Fast clock speed: 166, 150, 133, and 100 MHz
• Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns
• Pipelined data comparator
• Data input register load control by DEN
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% core power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• JTAG boundary scan
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low-profile JEDEC standard 100-pin TQFP package
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), Global Write (GW), and Data
Input Enable (DEN).
Asynchronous inputs include the Burst Mode Control (MODE),
the Output Enable (OE) and the Match Output Enable (MOE).
The data outputs (Q) and Match Output (MATCH), enabled by
OE and MOE respectively, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Data inputs are registered with Data Input Enable (DEN) and
chip enable pins (CE, CE2, and CE2). The outputs of the data
input registers are compared with data in the memory array
and a match signal is generated. The match output is gated
into a pipeline register and released to the match output pin at
the next rising edge of Clock (CLK).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to two bytes wide as controlled by the write control inputs. In-
dividual byte write allows individual byte to be written. WEL
controls DQ1–DQ9. WEH controls DQ10–DQ18. WEL and
WEH can be active only with BWE being LOW. GW being LOW
causes all bytes to be written.
The CY7C1359C/GVT71256T18 operates from a +3.3V pow-
er supply with output power supply being +2.5V or +3.3V. All
inputs and outputs are LVTTL compatible. The device is ideally
suited for address tag RAM for up to 8 MB secondary cache.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1359A-166
71256T36-6
3.5
310
20
7C1359A-150
71256T36-6.7
3.8
275
20
7C1359A-133
71256T36-7.5
4.0
250
20
7C1359A-100
71256T36-10
4.5
190
20
www.DataSheet4U.com
wwCw.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05120 Rev. **
Revised September 13, 2001
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CY7C1359A/GVT71256T18
Pin Descriptions (continued)
BGA Pins
6P
TQFP Pins
51
Name
MOE
7P, 6N, 6L, 7K,
6H, 7G, 6F, 7E,
6D, 1D, 2E, 2G,
1H, 2K, 1L, 2M,
1N, 2P
58, 59, 62, 63, 68,
69, 72, 73, 74, 8,
9, 12, 13, 18, 19,
22, 23, 24
5U 42
2U 38
3U 39
4U 43
4C, 2J, 4J, 6J, 4R 15, 41,65, 91
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54,
7J, 1M, 7M, 1U,
61, 70, 77
7U
1B, 7B, 1C, 7C,
2D, 4D, 7D, 1E,
6E, 2F, 1G, 6G,
2H, 7H, 3J, 5J,
1K, 6K, 2L, 4L,
7L, 2N, 1P, 1R,
5R, 7R, 1T, 4T, 6U
1-3, 6, 7, 14, 16,
25, 28-30, 56, 57,
66, 75, 78, 79, 95,
96
DQ1–
DQ18
TDO
TMS
TDI
TCK
VCC
VSS
VCCQ
NC
Type
Input
Input/
Output
Description
Match Output Enable: This active LOW asynchronous input
enables the MATCH output drivers.
Data Inputs/Outputs: Input data must meet setup and hold
times around the rising edge of CLK.
Output
Input
IEEE 1149.1 test output. LVTTL-level output.
IEEE 1149.1 test inputs. LVTTL-level inputs.
Supply
Ground
Power Supply: +3.3V –5% and +10%
Ground: GND
I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC)
- No Connect: These signals are not internally connected.
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Partial Truth Table for MATCH[2, 3, 4, 5, 6]
Operation
E
WE
DEN
MOE
OE MATCH DQ
READ Cycle
LHXXL - Q
WRITE Cycle
L L LXH - D
Fill WRITE Cycle
L L H X H - High-Z
COMPARE Cycle
L H L L H Output D
Deselected Cycle (MATCH Out)
H
X
X
L
X
H High-Z
Deselected Cycle
H
X
X
H
X
High-Z
High-Z
Notes:
2. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW.
3. E=L is defined as CE=LOW and CE2=LOW and CE2=HIGH. E =H is defined as CE=HIGH or CE2=HIGH or CE2=LOW. WE is defined as [BWE + WEL*WEH]*GW.
4. All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
Document #: 38-05120 Rev. **
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