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Número de pieza MC74HC4053A
Descripción (MC74HC4051A - MC74HC4053A) Analog Multiplexers/Demultiplexers
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MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Analog Multiplexers /
Demultiplexers
High−Performance Silicon−Gate CMOS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon−gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
across the complete power supply range (from VCC to VEE).
The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal−gate MC14051AB, MC14052AB and MC14053AB. The
Channel−Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.
Features
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V
Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
Low Noise
In Compliance With the Requirements of JEDEC Standard No. 7A
Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
Pb−Free Packages are Available*
http://onsemi.com
16
1
16
1
16
1
16
1
16
1
MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC405xAN
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
HC405xAG
AWLYWW
1
16
SOIC−16 WIDE
DW SUFFIX
CASE 751G
HC405xA
AWLYWWG
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HC40
5xA
ALYWG
G
1
SOEIAJ−16
F SUFFIX
CASE 966
16
74HC405xA
ALYWG
1
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 3
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Publication Order Number:
MC74HC4051A/D

1 page




MC74HC4053A pdf
MC74HC4051A, MC74HC4052A, MC74HC4053A
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Symbol
Parameter
Ron Maximum “ON” Resistance
Condition
Vin = VIL or VIH; VIS = VCC to
VEE; IS 2.0 mA
(Figures 1, 2)
VCC VEE −55 to 25°C 85°C 125°C Unit
4.5 0.0
4.5 − 4.5
6.0 − 6.0
190
120
100
240 280 W
150 170
125 140
Vin = VIL or VIH; VIS = VCC or
VEE (Endpoints); IS 2.0 mA
(Figures 1, 2)
4.5 0.0
4.5 − 4.5
6.0 − 6.0
150
100
80
190 230
125 140
100 115
DRon
Ioff
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIS = 1/2 (VCC − VEE);
IS 2.0 mA
Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 3)
4.5 0.0
4.5 − 4.5
6.0 − 6.0
6.0 − 6.0
30
12
10
0.1
35 40 W
15 18
12 14
mA
0.5 1.0
Maximum Off−ChannelHC4051A Vin = VIL or VIH;
Leakage Current,
HC4052A VIO = VCC − VEE;
Common Channel HC4053A Switch Off (Figure 4)
6.0 − 6.0
6.0 − 6.0
6.0 − 6.0
0.2
0.1
0.1
2.0 4.0
1.0 2.0
1.0 2.0
Ion Maximum On−ChannelHC4051A Vin = VIL or VIH;
Leakage Current, HC4052A Switch−to−Switch =
Channel−to−Channel HC4053A VCC − VEE; (Figure 5)
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
6.0 − 6.0
6.0 − 6.0
6.0 − 6.0
0.2
0.1
0.1
2.0 4.0 mA
1.0 2.0
1.0 2.0
Guaranteed Limit
VCC
V −55 to 25°C 85°C 125°C Unit
tPLH,
tPHL
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9)
2.0 270
3.0 90
4.5 59
6.0 45
320 350 ns
110 125
79 85
65 75
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0 40
3.0 25
4.5 12
6.0 10
60 70 ns
30 32
15 18
13 15
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0 160
3.0 70
4.5 48
6.0 39
200 220 ns
95 110
63 76
55 63
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0 245
3.0 115
4.5 49
6.0 39
315 345 ns
145 155
69 83
58 67
Cin Maximum Input Capacitance, Channel−Select or Enable Inputs
CI/O Maximum Capacitance
Analog I/O
(All Switches Off)
Common O/I: HC4051A
HC4052A
HC4053A
10 10 10 pF
35 35 35 pF
130 130 130
80 80 80
50 50 50
Feedthrough
1.0 1.0 1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D)
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Figure 13)*
HC4051A
HC4052A
HC4053A
45
80
45
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
5

5 Page





MC74HC4053A arduino
MC74HC4051A, MC74HC4052A, MC74HC4053A
+5V
+5V
ANALOG
16
ANALOG
+5V
ON
−5V SIGNAL
SIGNAL
−5V
6 11 TO EXTERNAL CMOS
7 10 CIRCUITRY 0 to 5V
8 9 DIGITAL SIGNALS
−5V
Figure 15. Application Example
VCC VCC VCC
Dx 16 Dx
ON/OFF
Dx Dx
VEE VEE
7
8
VEE
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
+5V
ANALOG
16
ANALOG
+5V
ON/OFF
VEE SIGNAL
SIGNAL
+5V
VEE
*
RRR
+5V
+5V
ANALOG
16
ANALOG
+5V
ON/OFF
VEE SIGNAL
SIGNAL
VEE
+5V
6 11
7 10
89
LSTTL/NMOS
CIRCUITRY
VEE * 2K R 10K
a. Using Pull−Up Resistors
6 11
7 10
89
VEE HCT
BUFFER
b. Using HCT Interface
LSTTL/NMOS
CIRCUITRY
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
A 11
LEVEL
SHIFTER
13 X0
14 X1
B 10
LEVEL
SHIFTER
15 X2
12 X3
C9
LEVEL
SHIFTER
1 X4
5 X5
ENABLE 6
LEVEL
SHIFTER
2 X6
4 X7
Figure 18. Function Diagram, HC4051A
3X
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