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What is STA015?

This electronic component, produced by the manufacturer "ST Microelectronics", performs the same function as "(STA015x) MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY".


STA015 Datasheet PDF - ST Microelectronics

Part Number STA015
Description (STA015x) MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
Manufacturers ST Microelectronics 
Logo ST Microelectronics Logo 


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STA015
STA015B STA015T
MPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
– All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
– All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
m– Lower sampling frequencies syntax exten-
osion, (not specified by ISO) called MPEG 2.5
.cDECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
SUPPORTING ALL THE MPEG 1 & 2
USAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:
t448, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III
eELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
eKbit/s
hADPCM CODEC CAPABILITIES:
– sample frequency from 8 kHz to 32 kHz
S– sample size from 8 bits to 32 bits
– encoding algorithm: DVI,
taITU-G726 pack (G723-24, G721,G723-40)
– Tone control and fast-forward capability
aEASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
.D(TQFP44 & LFBGA 64)
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
wBYPASS MODE FOR EXTERNAL AUDIO
SOURCE
wSERIAL BITSTREAM INPUT INTERFACE
wEASY PROGRAMMABLE ADC INPUT
SO28
TQFP44
LFBGA64
ORDERING NUMBER: STA015$ (SO28)
STA015T$ (TQFP44)
STA015B$ (LFBGA 8x8)
INDICATORS
I2C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERS
DESCRIPTION
The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decod-
ing Layer III compressed elementary streams, as
specified in MPEG 1 and MPEG 2 ISO standards.
The device decodes also elementary streams
compressed by using low sampling rates, as spec-
INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C
INTERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S AND
OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
March 2004
ified by MPEG 2.5. STA015 receives the input
mdata through a Serial input Interface. The decoded
osignal is a stereo, mono, or dual channel digital
.coutput that can be sent directly to a D/A converter,
Uby the PCM Output Interface.
t4This interface is software programmable to adapt
ethe STA015 digital output to the most common
eDACs architectures used on the market. The func-
htional STA015 chip partitioning is described in
SFig.1a and Fig.1b.
www.Data 1/55

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STA015 equivalent
STA015 STA015B STA015T
PIN DESCRIPTION
SO28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TQFP44
29
30
31
32
34
36
38
40
42
44
2
3
5
6
7
8
10
11
12
13
15
19
21
22
24
25
26
27
20
18
16
14
37
39
41
43
35
4
28
33
LFBGA64
B5
B4
A4
B3
A1
B2
D4
D1
E2
F2
H1
H3
F3
E4
G4
G5
F5
G6
G7
G8
F7
E7
C8
D7
A7
B6
A5
C5
C7
E6
F6
F8
C3
E3
D2
F1
C2
G3
C6
A2
Pin Name Type
Function
PAD Description
VDD_1
Supply Voltage
VSS_1
Ground
SDA
I/O i2C Serial Data +
Acknowledge
CMOS Input Pad Buffer
CMOS 4mA Output Drive
SCL
I I2C Serial Clock
CMOS Input Pad Buffer
SDI
I Receiver Serial Data
CMOS Input Pad Buffer
SCKR
I Receiver Serial Clock
CMOS Input Pad Buffer
BIT_EN
I Bit Enable
CMOS Input Pad Buffer
with pull up
SRC_INT/
SCK_ADC
I Interrupt Line/ADC Serial
Clock
CMOS Input Pad Buffer
SDO
O Transmitter Serial Data
(PCM Data)
CMOS 4mA Output Drive
SCKT
O Transmitter Serial Clock
CMOS 4mA Output Drive
LRCKT
O Transmitter Left/Right Clock CMOS 4mA Output Drive
OCLK
I/O Oversampling Clock for DAC CMOS Input Pad Buffer
CMOS 4mA Output Drive
VSS_2
Ground
VDD_2
Supply Voltage
VSS_3
Ground
VDD_3
Supply Voltage
PVDD
PLL Power
PVSS
PLL Ground
FILT
O PLL Filter Ext. Capacitor
Conn.
XTO
O Crystal Output
CMOS 4mA Output Drive
XTI I Crystal Input (Clock Input) Specific Level Input Pad
(see paragraph 2.1)
VSS_4
Ground
VDD_4
Supply Voltage
TESTEN
I Test Enable
CMOS Input Pad Buffer
with pull up
SDI_ADC
I ADC Data Input
CMOS Input Pad Buffer
RESET
I System Reset
CMOS Input Pad Buffer
with pull up
LRCK_ADC
I ADC left/Right Clock
CMOS Output Pad Buffer
IN_CLK/
DATA_REQ
O Buffered Output Clock/
Data Request Signal
CMOS 4mA Output Drive
IODATA[0]
IODATA[1]
IODATA[2]
I/O GPIO Data Line
I/O GPIO Data Line
I/O GPIO Data Line
CMOS 4mA Schmitt
Trigger
Bidir Pad Buffer
IODATA[3] I/O GPIO Data Line
IODATA[4] I/O GPIO Data Line
IODATA[5] I/O GPIO Data Line
IODATA[6] I/O GPIO Data Line
IODATA[7] I/O GPIO Data Line
GPIO_STROBE I/O GPIO Strobe Signal
GPSO_REQ O GPSO Request Signal
CMOS Output Pad Buffer
GPSO_SCKR I GPSO Serial Clock
CMOS Input Pad Buffer
GPSO_DATA O GPSO Serial Data
CMOS Output Pad Buffer
Note: In functional mode TESTEN must be connected to VDD,
5/55


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