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PDF MC74HC390 Data sheet ( Hoja de datos )
| Número de pieza | MC74HC390 | |
| Descripción | Dual 4-Stage Binary Ripple Counter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74HC390 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4-Stage Binary
MC54/74HC390
Ripple Counter with
÷ 2 and ÷ 5 Sections
High–Performance Silicon–Gate CMOS
J SUFFIX
CERAMIC PACKAGE
16 CASE 620–10
The MC54/74HC390 is identical in pinout to the LS390. The device inputs
1
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two independent 4–bit counters, each composed
N SUFFIX
of a divide–by–two and a divide–by–five section. The divide–by–two and
divide–by–five counters have separate clock inputs, and can be cascaded to
mimplement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.
Flip–flops internal to the counters are triggered by high–to–low transitions
oof the clock input. A separate, asynchronous reset is provided for each 4–bit
counter. State changes of the Q outputs do not occur simultaneously
.cbecause of internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used as clocks or strobes
except when gated with the Clock of the HC390.
U• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
t4• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
e• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
eNo 7A
h• Chip Complexity: 244 FETs or 61 Equivalent Gates
taSLOGIC DIAGRAM
a1, 15
.DCLOCK A
÷2
COUNTER
3, 13 QA
ww mCLOCK B 4, 12
÷5
COUNTER
5, 11
QB
6, 10
7, 9
QC
QD
w .co2,14
URESET
et4PIN 16 = VCC
ePIN 8 = GND
16
1
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
CLOCK Aa
RESET a
QAa
CLOCK Ba
QBa
QCa
QDa
GND
1
2
3
4
5
6
7
8
16 VCC
15 CLOCK Ab
14 RESET b
13 QAb
12 CLOCK Bb
11 QBb
10 QCb
9 QDb
FUNCTION TABLE
Clock
AB
Reset Action
XX
X
X
H Reset
÷ 2 and ÷ 5
L Increment
÷2
L Increment
÷5
www.DataSh10/95
© Motorola, Inc. 1995
1 REV 6
1 page  
EXPANDED LOGIC DIAGRAM
CLOCK A 1, 15
CQ
D RQ
3, 13 QA
CLOCK B 4, 12
CQ
DQ
R
5, 11 QB
MC54/74HC390
CQ
DQ
R
6, 10 QC
RESET 2, 14
C
D RQ
7, 9 QD
TIMING DIAGRAM
(QA Connected to Clock B)
0 1 2 3 4 5 6 78 90 1 2 3 4 5 6
CLOCK A
RESET
QA
QB
QC
QD
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74HC390.PDF ] | |
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