|
|
PDF MC74HC390A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC390A | |
| Descripción | Dual 4-Stage Binary Ripple Counter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MC74HC390A (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
MC74HC390A
Dual 4−Stage Binary Ripple
Counter with ÷ 2 and ÷ 5
Sections
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
MARKING
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit counters, each
composed of a divide−by−two and a divide−by−five section. The
mdivide−by−two and divide−by−five counters have separate clock
oinputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
.cFlip−flops internal to the counters are triggered by high−to−low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
Uoccur simultaneously because of internal ripple delays. Therefore,
t4decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
eFeatures
e• Output Drive Capability: 10 LSTTL Loads
h• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
S• Low Input Current: 1 mA
ta• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
aNo 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
.D• Pb−Free Packages are Available*
16
1
16
1
16
1
16
1
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC390AN
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
HC390AG
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HC
390A
ALYWG
G
1
SOEIAJ−16
F SUFFIX
CASE 966
16
74HC390A
ALYWG
1
w A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
w W, WW = Work Week
G = Pb−Free Package
w mG = Pb−Free Package
o(Note: Microdot may be in either location)
t4U.cORDERING INFORMATION
eSee detailed ordering and shipping information in the package
edimensions section on page 2 of this data sheet.
ataSh*For additional information on our Pb−Free strategy and soldering details, please
.Ddownload the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
www© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
June, 2005 − Rev. 3
MC74HC390A/D
1 page  
MC74HC390A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtrec
Parameter
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw Minimum Pulse Width, Clock A, Clock B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw Minimum Pulse Width, Reset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtf, tf Maximum Input Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
Guaranteed Limit
VCC
– 55 to
V 25_C v 85_C v 125_C Unit
2.0 25 30 40 ns
3.0 15 20 30
4.5 10 13 15
6.0 9
11 13
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
15 19
2.0 75
3.0 27
4.5 20
6.0 18
95 110 ns
32 36
24 30
22 28
2.0 1000
3.0 800
4.5 500
6.0 400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Clock A is the clock input to the ÷ 2 counter; Clock B is
the clock input to the ÷ 5 counter. The internal flip−flops are
toggled by high−to−low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip−flops, and forces QA
through QD low.
OUTPUTS
QA (Pins 3, 13)
Output of the ÷ 2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the ÷ 5 counter. QD is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi−quinary mode as in
Figure 5.
CLOCK
Q
tf
90%
50%
10% 10%
tw
90%
50%
10%
1/fmax
tPLH
tTLH
tr
tPHL
tTHL
Figure 3.
SWITCHING WAVEFORMS
VCC
RESET
GND
tPHL
Q
CLOCK
tw
50%
50%
trec
50%
Figure 4.
VCC
GND
VCC
GND
http://onsemi.com
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MC74HC390A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MC74HC390 | Dual 4-Stage Binary Ripple Counter |  Motorola Semiconductors |
| MC74HC390 | Dual 4-Stage Binary Ripple Counter | ON Semiconductor |
| MC74HC390A | Dual 4-Stage Binary Ripple Counter | ON Semiconductor |
| MC74HC390A | Dual 4-Stage Binary Ripple Counter | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |