UT6264B Datasheet PDF - Utron
| Part Number | UT6264B | |
| Description | 8K X 8 BIT LOW POWER CMOS SRAM | |
| Manufacturers | Utron | |
| Logo |  |
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UTRON
UT6264B
Rev 1.0
8K X 8 BIT LOW POWER CMOS SRAM
____________________________________________________________________________________________
FEATURES
The UT6264B is a 65,536-bit low power
Access time : 35/70ns (max.)
Low power consumption:
Operating : 60/40 mA (typical)
Standby :0.3 mA (typical) normal
CMOS static random access memory
organized as 8,192 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
2 µA (typical) L-version
1 µA (typical) LL-version
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
m Package : 28-pin 600 mil PDIP
o28-pin 330 mil SOP
.cFUNCTIONAL BLOCK DIAGRAM
The UT6264B is designed for high-speed
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.
The UT6264B operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible.
PIN CONFIGURATION
UA4
A3
t4A12 .
e.A7 ROW
A6 DECODER
eA5 .
A8
hA2
MEMORY ARRAY
256 ROWS × 256 COLUMNS
taSI/O1
...
...
I/O
CONTROL
I/O8
...
. ..
COLUMN I/O
COLUMN DECODER
aCE LOGIC
.DWE CONTROL
OE
A10 A9 A11 A1 A0
wPIN DESCRIPTION
VCC
VSS
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
28 Vcc
27 WE
26 NC
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
PDIP / SOP
wSYMBOL
A0 – A12
wI/O1 – I/O8
mCE
oWE
.cOE
UVCC
t4VSS
eNC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
taSheGENERAL DESCRIPTION
a_____________________________________________________________________________________________
.DUTRON TECHNOLOGY INC.
P80039
w1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
ww1
|
| |
 
UTRON
UT6264B
Rev 1.0
8K X 8 BIT LOW POWER CMOS SRAM
_____________________________________________________________________________________________
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
Address
CE
WE
DOUT
DIN
tAS
(4)
tWC
tAW
tCW
tWP
tWHZ
High-Z
tWR
tOW
tDW tDH
Data Valid
(4)
WRITE CYCLE 2 ( CE Controlled) (1,2,5)
tWC
Address
CE
WE
DOUT
tAW
tAS tCW
tWP
tWHZ
(4)
High-Z
tWR
tDW tDH
DIN
Data Valid
Notes :
1. WE or CE must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow
drivers
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
the I/O
5. If the CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high
impedance state.
6. tOW and tWHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80039
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for UT6264B electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ UT6264B.PDF Datasheet ] | |
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