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PDF UPD765A Data sheet ( Hoja de datos )
| Número de pieza | UPD765A | |
| Descripción | Single / Double Density Floppy-Disk Controller | |
| Fabricantes | NEC Electronics | |
| Logotipo |  |
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NEC
NEC Electronics Inc.
uPD765A/uPD765B
Single/Double Density
Floppy-Disk Controller
Description
The uPD765A/B is an LSI floppy disk controller (FDC)
chip which contains the circuitry and control functions
for interfacing a processor to 4 floppy disk drives. It is
capableof either IBM 3740singledensity format (FM), or
IBM System 34 double density format (MFM) including
double-sided recording. The uPD765A/B provides con-
trol signals which simplify the design of an external
phase-locked loop and write precompensation circuitry.
The FDC simplifies and handles most of the burdens as-
sociated with implementing a floppy disk interface.
Hand-shaking signals are provided in the uPD765A/B
which make DMA operation easy to incorporate with the
aid of an external DMA controller chip, such as the
uPD8257. The FDC will operate in eitherthe DMA or non-
DMA mode. In the non-DMA mode the FDC generates
interrupts to !he processor every time a data byte is to
be transferred. In the DMA mode, the processor need
only load the command into the FDC and all data
transfers occur under control of the FDC and DMA
controllers.
There are 16 commands which the uPD765A/uPD765B
will execute. Most of these commands require multiple
8-bit bytes to fully specify the operation which the
processor wishes the FDC to perform. The following
commands are available.
Read Data
Read ID
Specify
Read Diagnostic
Scan Equal
Scan High or Equal
Scan Low or Equal
Version
Read Deleted Data
Write Data
Write ID (Format Write)
Write Deleted Data
Seek
Recalibrate
Sense Interrupt Status
Sense Drive Status.
Ordering Information
Device Number
uPD765AC2
uPD765B
Package Type
40-pin plastic DIP
40-pin plastic DIP
Max Freq. of Operation
8 MHz
8 MHz
Features
Address mark detection circuitry is internal to the FDC
which simplifies the phase-locked loop and read elec-
tronics. The track stepping rate, head load time, and
head unload time are user-programmable. The
uPD765A/uPD765B
offers additional features such as
multi-track and multi-side read and write commands
and single and double density capabilities.
FM, MFM Control
Variable recording length: 128,256, .8192 bytes/
sector
IBM-compatible format (single- and double-
sided, single- and double-density)
Multi-sector and multi-track transfer capability
Drive up to 4 floppy or micro floppydisk drives
Data scan capability-will scan a single sector or
an entire cylinder comparing byte-for-byte host
memory and disk data
Data transfers in DMA or non-DMA mode
Parallel seek operations on up to four drives
Compatible with uPD8080/85, uPD8086/88,
and uPD780 (Z80@) microprocessors
V-series
Single-phase clock: 8 MHz maximum
3 +5V only
Z80 is a registered trademark of the Zilog Corporation
Pin Configuration
NECEL-000324
5-3
1 page  
NEC
DIFFERENCES BETWEEN ,uPD765A AND
uP D765B
The uPD765B is a functionally enhanced version of the
uPD765A.Differences are explained below.
Overrun Bit [OR]
In uPD765A, when executing a read- or write-type
command (except READ ID and SCAN types), the
result status OR bit is not set if there is an overrun on
the final byte of a sector. An improvement in the
uPD765B allows it to set the OR bit in any situation.
DRQ Reset
When an overrun occurs, the uPD765A needs DACK
input to reset DRQ. If DACK is not available, an
external DMA controller continues to operate even after
the FDC enters the R-Phase (Result Phase), and stored
result status may be transferred accidentally as ordinary
data.
On the other hand, the uPD765B resets DRQ auto-
matically just before the R-Phaseentry and independent
of the DACK input. See AC Characteristics for DRQ
reset timing.
Clock Synchronization
The uPD765B does not require synchronization
between the CLK and WCLK inputs.
Version Command
The Version command distinguishes the uPD765B
from other devices. The ST0 response to the Version
command is:
Part No.
ST0 Value
uPD765A
uPD765B
80H
90H
uPD765A/uPD765B
5-7
5 Page 
NEC
uPD765A/uPD765B
Table 3. Status Register Identification (cont)
Pin
NC. Name
Function
Status Register 3
D7 FT
(Fault)
This bit is used to indicate the status of the
fault signal from the FDD.
D6 WP
(Write Protected)
This bit is used to indicate the status of the
write protected signal from the FDD.
D56 RY
(Ready)
D4 TO
(Track 0)
This bit is used to Indicate the status of the
ready signal from the FDD.
This bit IS used to indicate the status of the
track 0 signal from the FDD.
03 TS
(Two-Side)
This bit IS used to indicate the status of the
two-side signal from the FDD.
D2 HD
(Head Address)
This bit is used to Indicate the status of the
side select signal to the FDD
D1 US1
(Unit Select 1)
This bit is used to Indicate the status of the
unit select 1 signal to the FDD.
D0 US0
(Unit Select 0)
This bit is used to indicate the status of the
unit select 0 signal to the FDD.
Note:
(1) CRC = Cyclic Redundancy Check
(2) IDR = Internal Data Register
(3) Cylinder (C) is described more fully in the Command Symbol
Description.
Command Sequence
The uPD765A/uPD765B is capable of performing 15 dif-
ferent commands. Each command is initiated by a
multibyte transfer from the processor, and the result af-
ter execution of the command may also be a multibyte
transfer back to the processor. Because of this multi-
byte interchange of information between the uPD765A/
uPD765B and the processor, it is convenient to consider
each command as consisting of three phases:
Command
Phase:
The FDC receives all information re-
quired to perform a particular opera-
tion from the processor.
Execution
Phase:
The FDC performs the operation it
was instructed to do.
Result Phase:
After completion of the operation,
status and other housekeeping infor-
mation are made available to the
processor.
Table 4 shows the required preset parameters and
results for each command. Most commands require 9
command bytes and return 7 bytes during the result
phase. The “W” to the left of each byte indicates a com-
mand phase byte to be written, and an “R” indicates a
result byte. The definitions of other abbriviations used
in table are given in the Command Symbol Description
table.
Command Symbol Description
Name Function
A0
(Address Line 0)
A0 controls selection of main status register
(A0=0) or data register (A0= 1).
C
(Cylmder Number)
C stands for the current /selected cylinder
(track) numbers 0 through 76 of the medium
D
(Data)
D stands for the data pattern which is going to be
written into a sector during WRITE ID operation
D7-D0
(Data Bus)
8-bit data bus, where D7 stands for a most
significant bit, and D0 s t a n d s f o r a l e a s t
significant bit.
DTL
(Data Length)
When N is defined as 00. DTL stands for the data
length which users are going to read out or write
into the sector
EOT
(End of Track)
EOT stands for the final sector number on a cylin-
der Durmg read or write operations, FDC will stop
data transfer after a sector number equal to EOT
GPL
(Gap Length)
GPL stands for the length of gap 3. During Read /
Write commands this value determines the num-
ber of bytes that VCO sync will stay low after two
CRC bytes During Format command it deter-
mines the size of gap 3
H
(Head Address)
H stands for the logical head number 0 or 1. as
specified in ID field
HD(Head)
HD stands for a the physical head number 0 or 1
and controls the polarity of pin 27 (H = HD in all
command words )
HLT
(Head Load Time)
HLT stands for the head load time in the FDD (2 to
254 ms in 2 ms Increments).
HUT
(Head Unload Time)
HUT stands for the head unload time after a Read
or Write operation has occurred (16 to 240 ms in
16 ms Increments)
MF
(FM or MFM Mode)
If MF IS low, FM mode IS selected, and if it is high,
MFM mode IS selected
MT
(Multitrack)
IF MT is high, a multitrack operation IS per-
formed If MT = 1 after finishing read/write oper-
ation on siude 0. FDC will automatically start
searching for sector 1 on side 1
N
(Number)
N stands for the number of data bvtes written in a
sector
NCN
(New Cylinder Number)
NCN stands for a new cylinder number which is
going to be reached as a result of the seek opera-
tion; desired position of head
ND
(Non-DMA Mode)
ND stands for operation in the non-DMA mode
P C N PCN stands for the cylinder number at the
(Present Cylinder Number) completion of Sense Interrupt Status command,
position of head at present time
R
[Record)
R stands for the sector number which will be read
or written
R/W
(Read/Write)
R/W stands for either Read (R) or Write (W)
signal
SC
(Sector)
SC indicates the number of sectors per cylinder
SK
(Skip)
SK stands for skip deleted data address mark
5-13
11 Page | ||
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| PDF Descargar | [ Datasheet UPD765A.PDF ] | |
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