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PDF UPD703116 Data sheet ( Hoja de datos )
| Número de pieza | UPD703116 | |
| Descripción | 32-Bit Single-Chip Microcontrollers | |
| Fabricantes | NEC Electronics | |
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User’s Manual
V850E/IA1
32-Bit Single-Chip Microcontrollers
Hardware
µPD703116
µPD703116(A)
µPD703116(A1)
µPD70F3116
µPD70F3116(A)
µPD70F3116(A1)
Document No. U14492EJ4V1UD00 (4th edition)
Date Published April 2004 N CP(K)
Printed in Japan
1999, 2002
1 page  
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
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obtain a list of authorized representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
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components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
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Tel: 408-588-6000
800-366-9782
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J04.1
User’s Manual U14492EJ4V1UD
5
5 Page 
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
Transfer Target........................................................................................................................ 142
6.7.1 Transfer type and transfer target ................................................................................................142
6.7.2 External bus cycles during DMA transfer (two-cycle transfer) ....................................................143
DMA Channel Priorities .......................................................................................................... 143
Next Address Setting Function ............................................................................................. 143
DMA Transfer Start Factors ................................................................................................... 145
Forcible Interruption............................................................................................................... 146
DMA Transfer End................................................................................................................... 146
Forcible Termination .............................................................................................................. 146
6.13.1 Restriction related to DMA transfer forcible termination .............................................................146
Times Related to DMA Transfer............................................................................................. 148
Precautions.............................................................................................................................. 148
6.15.1 Interrupt factors .........................................................................................................................149
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION..................................................150
7.1 Features ................................................................................................................................... 150
7.2 Non-Maskable Interrupt.......................................................................................................... 153
7.2.1 Operation ...................................................................................................................................154
7.2.2 Restore.......................................................................................................................................156
7.2.3 Non-maskable interrupt status flag (NP) ....................................................................................157
7.2.4 Edge detection function..............................................................................................................157
7.3 Maskable Interrupts ................................................................................................................ 158
7.3.1 Operation ...................................................................................................................................158
7.3.2 Restore.......................................................................................................................................160
7.3.3 Priorities of maskable interrupts .................................................................................................161
7.3.4 Interrupt control register (xxICn).................................................................................................165
7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) ..........................................................................168
7.3.6 In-service priority register (ISPR) ...............................................................................................169
7.3.7 Maskable interrupt status flag (ID)..............................................................................................170
7.3.8 Interrupt trigger mode selection..................................................................................................170
7.4 Software Exception................................................................................................................. 179
7.4.1 Operation ...................................................................................................................................179
7.4.2 Restore.......................................................................................................................................180
7.4.3 Exception status flag (EP) ..........................................................................................................181
7.5 Exception Trap ........................................................................................................................ 182
7.5.1 Illegal opcode definition..............................................................................................................182
7.5.2 Debug trap .................................................................................................................................184
7.6 Multiple Interrupt Servicing Control ..................................................................................... 186
7.7 Interrupt Response Time........................................................................................................ 187
7.8 Periods in Which Interrupts Are Not Acknowledged .......................................................... 189
CHAPTER 8 CLOCK GENERATION FUNCTION ...............................................................................190
8.1 Features ................................................................................................................................... 190
8.2 Configuration .......................................................................................................................... 190
8.3 Input Clock Selection ............................................................................................................. 191
8.3.1 Direct mode ................................................................................................................................191
8.3.2 PLL mode...................................................................................................................................191
8.3.3 Peripheral command register (PHCMD).....................................................................................192
User’s Manual U14492EJ4V1UD
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD703116.PDF ] | |
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