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PDF MC74HC237 Data sheet ( Hoja de datos )
| Número de pieza | MC74HC237 | |
| Descripción | 1-of-8 Decoder/Demultiplexer with Address Latch | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-8 Decoder/Demultiplexer
with Address Latch
High–Performance Silicon–Gate CMOS
The MC74HC237 is identical in pinout to the LS137, but has noninverting
outputs. The device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.
The HC237 decodes a three–bit Address to one–of–eight active–high
outputs. The device has a transparent latch for storage of the Address. Two
Chip Selects, one active–low and one active–high, are provided to facilitate
the demultiplexing, cascading, and chip–selecting functions.
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using one of the Chip
Selects as a data input while holding the other one active.
The HC237 is the noninverting version of the HC137.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No 7A
• Chip Complexity: 156 FETs or 39 Equivalent Gates
LOGIC DIAGRAM
A0 1
ADDRESS
INPUTS
A1
2
A2 3
TRANSPARENT
LATCH
LATCH 4
ENABLE
1–OF–8
DECODER
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
7 Y7
ACTIVE–
HIGH
OUTPUTS
MC74HC237
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
A0
A1
A2
LATCH ENABLE
CS2
CS1
Y7
GND
1
2
3
4
5
6
7
8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
FUNCTION TABLE
CHIP- CS1
SELECT
INPUTS CS2
6
5
PIN 16 = VCC
PIN 8 = GND
Inputs
Outputs
LE CS1 CS2 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H XXX L L L L L L L L
X L X XXX L L L L L L L L
L H L LLLHL L L L L L L
L H L LLH L H L L L L L L
L H L LHL L L H L L L L L
L H L LHH L L L H L L L L
L H L HLL L L L L H L L L
L H L HLH L L L L L H L L
L H L HHL L L L L L L H L
L H L HHH L L L L L L L H
H H L XXX
*
* = Depends upon the Address previously applied while LE was
at a low level.
10/95
© Motorola, Inc. 1995
1 REV 6
1 page  
A0 1
A1 2
A2 3
LATCH 4
ENABLE
CS1 6
CS2 5
EXPANDED LOGIC DIAGRAM
MC74HC237
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
7 Y7
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MC74HC237.PDF ] | |
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