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PDF MT90733 Data sheet ( Hoja de datos )
| Número de pieza | MT90733 | |
| Descripción | CMOS DS3 Framer (DS3F) | |
| Fabricantes | Mitel Networks Corporation | |
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CMOS MT90733
® DS3 Framer (DS3F)
Advance Information
Features
• DS3 payload access in either bit-serial or
nibble-parallel mode
• C-bit parity or M13 operating mode
• Separate interface for C-bits
• Detect and generate DS3 AIS, and idle signals
• Transmit reference generator for serial
operation
• Transmit and receive FEAC channel under
software control
• Transmit single errors: framing, FEBE, C-bit
parity, and P-bit parity
• FEBE, C-bit and P-bit performance counters
• Transmit-to-Receive and Receive-to-Transmit
loopbacks
Applications
• Subrate multiplexing
• Wideband data or video transport
• DS3 monitor and test
• Channel extenders
ISSUE 1
May 1995
Ordering Information
MT90733AP 68 Pin PLCC
-40° to 85°C
Description
The MT90733 DS3 Framer (DS3F) is designed for
mapping broadband payloads into the DS3 frame for-
mat, which meets ANSI’s T1.107-1988 and supple-
ment T1.107a-1990.
Although the C-bit parity format is recommended, the
DS3F can also operate in the M13 mode. In the C-bit
parity format, the DS3F provides a separate interface
for selected C-bits. The DS3F also provides software
access for transmitting and receiving the FEAC chan-
nel, and generates and detects DS3 AIS, DS3 idle, P-
bit parity and C-bit parity. In addition, performance
counters are provided, as well as the ability to gener-
ate single framing, FEBE, C-bit parity and P-bit parity
errors. The payload interface is selectable through
software as either a bit-serial or nibble-parallel format.
X1
X2
FE
D3RD
D3RC
CRD
CRCK
CRF
CRDCC
STUFC
STUFD
AD(7-0)
WR
RD
ALE
SEL
OENA
FORCEOE
CXD
CXCK
CXF
CXDCC
D3TD
D3TC
FORCECP
FORCEPP
FORCFEBE
Line Side
U.S. Patent Number 5040170
DS3
Receive
µP I/O
Receive
DS3
Interpreter
Terminal Side
Output
Transmit
Frame
Reference
Generator
DS3
Send
Input
Transmit
Figure 1 - Functional Block Diagram
Serial Parallel
N.C.
N.C.
N.C.
RDS
RCS
RCG
RFS
RNIB3
RNIB2
RNIB1
RNIB0
RCN
N.C.
RFN
TDOUT
TCG
TFOUT
TCOUT
TFIN
TCIN
N.C.
N.C.
XCK
XFSI
XDS
N.C.
N.C.
N.C.
XFNO
XCN
XCK
N.C.
XNIB3
XNIB2
XNIB1
XNIB0
5-23
1 page  
Advance Information
CMOS MT90733
Other Signals
Pin #
Name I/O/P
Description
7
TEST
I Test Pin: Leave open.
9
OENA
O Overhead Enable. An active high signal that enables an overhead error to be
introduced into the overhead bit in the next 85th group by placing a low on the
FORCEOE lead.
11 X1 O DS3 Received X-Bit 1. An output indication of the state of the first X-bit
received in the DS3 frame.
13 X2 O DS3 Received X-Bit 2. An output indication of the state of the second X-bit
received in the DS3 frame (bit 680).
15
STUFD
O Stuff Data Status. This output signal provides an indication of the state of the
stuff opportunity bit from the received DS3F frame.
16
STUFC
O Stuff Clock. Provided for clocking out the stuff opportunity bit state.
43 FE O Framing Error Indication. An active high signal is generated when a framing
error is detected while in frame alignment. The framing error indication is held
active low when a DS3 out of frame alarm occurs.
49
TFIN
I Optional Framing Input Pulse. Not required for normal operation.
54 FORCEOE I Force DS3 Overhead Bit Error. An active low input signal used in conjunction
with the overhead enable signal (OENA) for introducing an overhead bit error
in the next transmitted 85-bit group.
55 FORCEPP I Force P-Bit Parity Error. An active low input signal generates and transmits a
P-bit error by inverting both P-bits.
57 FORCECP I Force C-Bit Parity Error. An active low input signal generates and transmits a
C-bit parity error when operating in the C-bit parity mode.
61 FORCFEBE I
Note: I = Input; O = Output; P = Power
Force FEBE Error. An active low input signal generates and transmits a far
end block error (FEBE) when operating in the C-bit parity mode.
Microprocesssor Interface
Pin #
Name I/O/P
Description
8
SEL
I Microprocessor Select. A low enables the processor to access the DS3F
memory map for control, status and alarm information.
10
ALE
I Address Latch Enable. An active high input signal is used by the processor
to hold an address stable during a read/write bus cycle on the falling edge.
12 RD I Read. An active low input signal generated by the processor for reading the
registers which reside in the DS3F memory map.
14 WR I Write. An active low input signal generated by the processor for writing to the
registers which reside in the memory map.
18-21
23-26
AD(7-4)
AD(3-0))
I/O
Note: I = Input; O = Output; P = Power
Address/Data Bus. These leads constitute the time multiplexed address and
data bus for accessing the registers which reside in the DS3F memory map.
5-27
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| PDF Descargar | [ Datasheet MT90733.PDF ] | |
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