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PDF 74LVT16374 Data sheet ( Hoja de datos )
| Número de pieza | 74LVT16374 | |
| Descripción | Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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January 1999
Revised June 2005
74LVT16374 • 74LVTH16374
Low Voltage 16-Bit D-Type Flip-Flop
with 3-STATE Outputs
General Description
The LVT16374 and LVTH16374 contain sixteen non-invert-
ing D-type flip-flops with 3-STATE outputs and is intended
for bus oriented applications. The device is byte controlled.
A buffered clock (CP) and Output Enable (OE) are com-
mon to each byte and can be shorted together for full 16-bit
operation.
The LVTH16374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT16374 and LVTH16374
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16374),
also available without bushold feature (74LVT16374)
s Live insertion/extraction permitted
s Power Up/Power Down high impedance provides
glitch-free bus loading
s Outputs source/sink 32 mA/64 mA
s Functionally compatible with the 74 series 16374
s Latch-up performance exceeds 500 mA
s ESD performance:
Human-body model ! 2000V
Machine model ! 200V
Charged-device model ! 1000V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number Package Number
Package Description
74LVT16374G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVT16374MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16374MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16374G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH16374MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16374MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation DS012022
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Symbol
Parameter
ICCH
ICCL
ICCZ
ICCZ
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
VCC
T A 40qC to 85qC
Units
(V) Min Max
3.6
0.19
mA
3.6 5 mA
3.6
0.19
mA
3.6
0.19
mA
'ICC
Increase in Power Supply Current
(Note 8)
3.6
0.2 mA
Note 5: Applies to bushold versions only (74LVTH16374).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
Outputs HIGH
Outputs LOW
Outputs Disabled
VCC d VO d 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 9)
Symbol
Parameter
VCC TA 25qC
(V) Min Typ Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
3.3
3.3
0.8
0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL 50 pF, RL 500:
(Note 10)
(Note 10)
AC Electrical Characteristics
Symbol
Parameter
TA 40qC to 85qC, CL 50 pF, RL 500:
VCC 3.3V r 0.3V
VCC 2.7V
Units
Min Max Min Max
fMAX
Maximum Clock Frequency
160 160 MHz
tPHL Propagation Delay
tPLH CP to On
1.9 4.3 1.9 4.6
1.6 4.5 1.6 5.2
ns
tPZL
tPZH
Output Enable Time
1.3 4.4 1.3 5.0
1.0 4.5 1.0 5.4
ns
tPLZ
tPHZ
Output Disable Time
1.5 4.6 1.5 4.8
2.0 5.0 2.0 5.4
ns
tS Setup Time
1.8 2.0
ns
tH Hold Time
0.8 0.1
ns
tW Pulse Width
3.0 3.0
ns
tOSHL
tOSLH
Output to Output Skew (Note 11)
1.0 1.0
ns
1.0 1.0
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
COUT
Output Capacitance
Note 12: Capacitance is measured at frequency f
VCC Open, VI 0V or VCC
VCC 3.0V, VO 0V or VCC
1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74LVT16374.PDF ] | |
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