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PDF SPT7850 Data sheet ( Hoja de datos )
| Número de pieza | SPT7850 | |
| Descripción | 10-BIT / 20 MSPS / 140 mW A/D CONVERTER | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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SPT7850
10-BIT, 20 MSPS, 140 mW A/D CONVERTER
FEATURES
APPLICATIONS
TECHNICAL DATA
JUNE 15, 2001
• Monolithic 20 MSPS converter
• 140 mW power dissipation
• On-chip track-and-hold
• Single +5 V power supply
• TTL/CMOS outputs
• 5 pF input capacitance
• Low cost
• Tri-state output buffers
• High ESD protection: 3,500 V minimum
• Selectable +3 V or +5 V logic I/O
• All high-speed applications where low power
dissipation is required
• Video imaging
• Medical imaging
• IR imaging
• Scanners
• Digital communications
GENERAL DESCRIPTION
The SPT7850 is a 10-bit monolithic, low-cost, ultralow-
power analog-to-digital converter capable of minimum
word rates of 20 MSPS. The on-chip track-and-hold func-
tion assures very good dynamic performance without the
need for external components. The input drive require-
ments are minimized due to the SPT7850’s low input
capacitance of only 5 pF.
Power dissipation is extremely low at only 140 mW typical
(165 mW maximum) at 20 MSPS with a power supply of
+5.0 V. The digital outputs are +3 V or +5 V, and are user
selectable. The SPT7850 is pin-compatible with an entire
family of 10-bit, CMOS converters (SPT7835/40/50/55/60/
61), which simplifies upgrades. The SPT7850 has incorpo-
rated proprietary circuit design* and CMOS processing
technologies to achieve its advanced performance. Inputs
and outputs are TTL/CMOS-compatible to interface with
TTL/CMOS logic systems. Output data format is straight
binary.
The SPT7850 is available in 28-lead 300 mil PDIP and
32-lead small (7 mm square) TQFP packages over the
commercial temperature range, and in a 28-lead SOIC
package over the industrial temperature range.
*Patent pending
BLOCK DIAGRAM
AIN
1:8
Mux
CLK In
Enable
Data
Valid
P1
...P2
Timing
and P7
Control
P8
Ref
In
ADC Section 1
T/H
Auto-
Zero
CMP
...ADC Section 2
ADC Section 7
ADC Section 8
T/H
Auto-
Zero
CMP
11-Bit
SAR
11
DAC
...
11-Bit
SAR
11
DAC
Reference Ladder
VREF
11
... 11
11
11
11-Bit
8:1
Mux/
Error
Correction
D10 Overrange
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
1 page  
Figure 1A – Timing Diagram 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
ANALOG IN
CLOCK IN
SAMPLING CLOCK
(Internal)
DIGITAL OUT
INVALID
VALID
1 2 3 4 5 6 7 8 9 10 11
DATA VALID
Figure 1B – Timing Diagram 2
tC
tCH tCL
tCLK
CLOCK
IN
tOD
DATA
OUTPUT
Data 0
Data 1
DATA
VALID
tS
tDAV
tDAV
Data 2
Table I – Timing Parameters
DESCRIPTION
PARAMETERS
Conversion Time
tC
Clock Period
tCLK
Clock High Duty Cycle
tCH
Clock Low Duty Cycle
tCL
Clock to Output Delay (15 pF Load)
tOD
DAV Pulse Width
tDAV
Clock to DAV
tS
MIN
2*tCLK
25
40
40
15
16
TYP
50
50
20
tCLK
21
MAX
60
60
25
26
UNITS
ns
ns
%
%
ns
ns
ns
SPT7850
5 6/15/01
5 Page 
28
1
B
C
A
D
H
PACKAGE OUTLINES
28-Lead SOIC
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.699
0.709
17.75
18.01
B
0.005
0.011
0.13
0.28
IH C
0.050 typ
1.27 typ
D 0.018 typ
0.46 typ
E
0.0077 0.0083
0.20
0.21
F
0.090
0.096
2.29
2.44
G
0.031
0.039
0.79
0.99
H
0.396
0.416
10.06
10.57
I
0.286
0.292
7.26
7.42
F
G
E
CD
A
B
EF
32-Lead TQFP
GH
I
J
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
L
INCHES
MIN MAX
0.346
0.362
0.272
0.280
0.346
0.362
0.272
0.280
0.031 typ
0.012
0.016
0.053
0.057
0.002
0.006
0.037
0.041
0.007
0° 7°
0.020
0.030
MILLIMETERS
MIN MAX
8.80 9.20
6.90 7.10
8.80 9.20
6.90 7.10
0.80 BSC
0.30 0.40
1.35 1.45
0.05 0.15
0.95 1.05
0.17
0° 7°
0.50 0.75
K
L
SPT7850
11 6/15/01
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SPT7850.PDF ] | |
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