MC74AC377 Datasheet PDF - ON Semiconductor
Part Number | MC74AC377 | |
Description | Octal D Flip-Flop | |
Manufacturers | ON Semiconductor | |
Logo | ||
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Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
• Buffered Common Clock
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ACT377 Has TTL Compatible Inputs
• MSL = 1 for all Surface Mount
• Chip Complexity: 292 FETs or 73 Gates
• These are Pb−Free Devices
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SOIC−20W
DW SUFFIX
CASE 751D
1
TSSOP−20
DT SUFFIX
CASE 948E
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
CE O0 D0 D1 O1 O2 D2 D3 O3 GND
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
PIN NAMES
PIN
D0−D7
CE
Q0−Q7
CP
FUNCTION
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 10
1
D0 D1 D2 D3 D4 D5 D6 D7
CP
CE
O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
Publication Order Number:
MC74AC377/D
|
|
MC74AC377, MC74ACT377
74ACT − DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
VIH Minimum High Level Input Voltage 4.5
5.5
TA = +255C
TA =
−405C to +855C
Typ Guaranteed Limits
1.5 2.0
1.5 2.0
2.0
2.0
VIL
Maximum Low Level Input Voltage 4.5
1.5
0.8
5.5 1.5
0.8
0.8
0.8
VOH Minimum High Level Output
Voltage
4.5 4.49
5.5 5.49
4.4
5.4
4.5 − 3.86
5.5 4.86
VOL Maximum Low Level Output
Voltage
4.5 0.001
5.5 0.001
0.1
0.1
4.5 − 0.36
5.5 0.36
IIN Maximum Input Leakage Current 5.5 − ±0.1
DICCT Additional Max ICC/Input
5.5 0.6
−
IOLD
IOHD
†Minimum Dynamic Output Current 5.5
−
−
ICC Maximum Quiescent Supply
Current
5.5 −
8.0
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
1.5
75
−75
80
Unit Conditions
V
VOUT = 0.1 V
or
VCC − 0.1 V
V
VOUT = 0.1 V
or
VCC − 0.1 V
V IOUT = −50 mA
V *VIN = VIL or VIH −24 mA
IOH −24 mA
V IOUT = 50 mA
V *VIN = VIL or VIH −24 mA
IOH −24 mA
mA VI = VCC, GND
mA VI = VCC − 2.1 V
mA VOLD = 1.65 V Max
VOHD = 3.85 V Min
mA VIN = VCC or GND
74ACT − AC CHARACTERISTICS For Figures and Waveforms — See Figures 4, 5, and 6.
Symbol
Parameter
fmax Maximum Clock Frequency
tPLH Propagation Delay
tPHL Propagation Delay
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
VCC*
(V)
CP to Qn
CP to Qn
5.0
5.0
5.0
TA = +25°C CL = 50 pF
Min Typ Max
140 −
−
3.0 − 9.0
3.5 − 10
TA = −40°C to +85°C
CL = 50 pF
Min Max
125 −
2.5 10
2.5 11
Unit
MHz
ns
ns
74ACT − AC OPERATING REQUIREMENTS
Symbol
Parameter
ts Setup Time, HIGH or LOW Dn to CP
th Hold Time, HIGH or LOW Dn to CP
ts Setup Time, HIGH or LOW CE to CP
th Hold Time, HIGH or LOW CE to CP
tw CP Pulse Width HIGH or LOW
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
VCC*
(V)
5.0
5.0
5.0
5.0
5.0
TA = +25°C CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Typ Guaranteed Minimum
− 4.5
5.5
− 1.0
1.0
− 4.5
5.5
− 1.0
1.0
− 4.0
4.5
Unit
ns
ns
ns
ns
ns
CAPACITANCE
Symbol
Parameter
CIN Input Capacitance
CPD Power Dissipation Capacitance
Value Typ
4.5
90
Unit
pF
pF
Test Conditions
VCC = 5.0 V
VCC = 5.0 V
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