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PDF ADCMP565 Data sheet ( Hoja de datos )
| Número de pieza | ADCMP565 | |
| Descripción | Dual Ultrafast Voltage Comparator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
300 ps propagation delay input to output
50 ps propagation delay dispersion
Differential ECL compatible outputs
Differential latch control
Robust input protection
Input common-mode range −2.0 V to +3.0 V
Input differential range ±5 V
Power supply sensitivity greater than 65 dB
200 ps minimum pulsewidth
5 GHz equivalent input rise time bandwidth
Typical output rise/fall of 160 ps
SPT 9689 replacement
APPLICATIONS
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers and signal restoration
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Clock drivers
Automatic test equipment
Dual Ultrafast
Voltage Comparator
ADCMP565
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP565
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
Figure 1.
02820-0-001
GENERAL DESCRIPTION
The ADCMP565 is an ultrafast voltage comparator fabricated
on Analog Devices’ proprietary XFCB process. The device
features 300 ps propagation delay with less than 50 ps overdrive
dispersion. Overdrive dispersion, a particularly important
characteristic of high speed comparators, is a measure of the
difference in propagation delay under differing overdrive
conditions.
A fast, high precision differential input stage permits consis-
tent propagation delay with a wide variety of signals in the
common-mode range from −2.0 V to +3.0 V. Outputs are
complementary digital signals fully compatible with ECL 10 K
and 10 KH logic families. The outputs provide sufficient drive
current to directly drive transmission lines terminated in 50 Ω
to −2 V. A latch input is included, which permits tracking,
track-and-hold, or sample-and-hold modes of operation.
The ADCMP565 is available in a 20-lead PLCC package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2. ADCMP565 Absolute Maximum Ratings
Parameter
Rating
Supply
Voltages
Positive Supply Voltage
(VCC to GND)
Negative Supply Voltage
(VEE to GND)
Ground Voltage Differential
−0.5 V to +6.0 V
−6.0 V to +0.5 V
−0.5 V to +0.5 V
Input
Voltages
Input Common-Mode
Voltage
−3.0 V to +4.0 V
Differential Input Voltage
−7.0 V to +7.0 V
Input Voltage,
Latch Controls
VEE to 0.5 V
Output
Output Current
30 mA
Temperature Operating Temperature,
Ambient
−40°C to +85°C
Operating Temperature,
Junction
125°C
Storage Temperature Range −55°C to +125°C
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ADCMP565
THERMAL CONSIDERATIONS
The ADCMP565 20-lead PLCC package option has a θJA
(junction-to-ambient thermal resistance) of 89.4°C/W in
still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
5 Page 
TYPICAL APPLICATION CIRCUITS
VIN
VREF
ADCMP565
OUTPUTS
LATCH
ENABLE
INPUTS
–2.0V
ALL RESISTORS 50Ω
Figure 7. High Speed Sampling Circuits
02820-0-007
+VREF
VIN
ADCMP565
OUTPUTS
–VREF
ADCMP565
LATCH
ENABLE
INPUTS
–2.0V
ALL RESISTORS 50Ω
02820-0-008
Figure 8. High Speed Window Comparator
VIN
ADCMP565
OUTPUTS
VREF
R1
R2
–2.0V
ALL RESISTORS 50Ω
02820-0-009
Figure 9. Hysteresis Using Positive Feedback
ADCMP565
VIN
ADCMP565
OUTPUTS
HYSTERESIS
VOLTAGE
450Ω
–2.0V
ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED
02820-0-010
Figure 10. Hysteresis Using Latch Enable Input
30Ω 50Ω
VIN
ADCMP565
30Ω 50Ω
127Ω
127Ω
–5.2V
02820-0-011
Figure 11. How to Interface an ECL Output to an
Instrument with a 50 Ω to Ground Input
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADCMP565.PDF ] | |
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