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PDF GS820E32A Data sheet ( Hoja de datos )
| Número de pieza | GS820E32A | |
| Descripción | 64K x 32 / 2M Synchronous Burst SRAM | |
| Fabricantes | GSI Technology | |
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GS820E32AT/Q-150/138/133/117/100/66
TQFP, QFP
Commercial Temp
Industrial Temp
64K x 32
2M Synchronous Burst SRAM
150Mhz - 66Mhz
9ns - 18ns
3.3V VDD
3.3V & 2.5V I/O
Features
• FT pin for user configurable flow through or pipelined operation.
• Dual Cycle Deselect (DCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or QFP package.
-150 -138 -133 -117 -100 -66
Pipeline tCycle 6.6ns 7.25ns 7.5ns 8.5ns 10ns 12.5ns
3-1-1-1 tKQ 3.8ns 4ns 4ns 4.5 5ns 6ns
IDD 270mA 245mA 240mA 210mA 180mA 150mA
Flow tCycle 10.5ns 15ns 15ns 15ns 15ns 20ns
Through tKQ 9ns 9.7ns 10ns 11ns 12ns 18ns
2-1-1-1 IDD 170mA 120mA 120mA 120mA 120mA 95mA
Functional Description
Applications
The GS820E32A is a 2,097,152 bit high performance synchronous
SRAM with a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU’s, the device now finds application in synchronous
SRAM applications ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-
BGA). Holding the FT mode pin/bump low, places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
DCD Pipelined Reads
The GS820E32A is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the same
degree as read commands. DCD RAMs hold the deselect command
for one full cycle and then begin turning off their outputs just after the
second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS820E32A operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)
pins are used to de-couple output noise from the internal circuit.
Rev: 1.04 3/2000
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
E
1 page  
GS820E32AT/Q-150/138/133/117/100/66
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
H or NC
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ H
Active
Standby, IDD = ISB
Note:
There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00 01 10 11
2nd address
01 10 11 00
3rd address
10 11 00 01
4th address
11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00 01 10 11
2nd address
01 00 11 10
3rd address
10 11 00 01
4th address
11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
GW BW
BA
BB
BC
BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte A
H
L
L
H
H
H 2, 3
Write byte B
H
L
H
L
H
H 2, 3
Write byte C
H
L
H
H
L
H 2, 3, 4
Write byte D
H
L
H
H
H
L 2, 3, 4
Write all bytes
H
L
L
L
L
L 2, 3, 4
Write all bytes
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.04 3/2000
5/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
E
5 Page 
GS820E32AT/Q-150/138/133/117/100/66
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
2.3V
0.2V
1V/ns
1.25V
1.25V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.
4. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
Output Load 2
2.5V
50Ω 30pF*
DQ 225Ω
VT=1.25V
* Distributed Test Jig Capacitance
5pF* 225Ω
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
ZZ Input Current
Mode Pin Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
Symbol Test Conditions
IIL VIN = 0 to VDD
IINZZ
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
IINM
VDD ≥ VIN ≥ VIL
0V ≤ VIN ≤ VIL
IOL
Output Disable,
VOUT = 0 to VDD
VOH IOH = - 4mA, VDDQ=2.375V
VOH IOH = - 4mA, VDDQ=3.135V
VOL IOL = 4mA
Min
-1uA
-1uA
-1uA
-300uA
-1uA
-1uA
1.7V
2.4V
Max
1uA
1uA
300uA
1uA
1uA
1uA
0.4V
Rev: 1.04 3/2000
11/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
E
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet GS820E32A.PDF ] | |
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