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PDF MC74HC646 Data sheet ( Hoja de datos )
| Número de pieza | MC74HC646 | |
| Descripción | Octal 3-State Bus Transeceivers and D Flip-Flops | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74HC646 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Bus Transceivers
and D Flip-Flops
High–Performance Silicon–Gate CMOS
The MC54/74HC646 is identical in pinout to the LS646. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
These devices are bus transceivers with D flip–flops. Depending on the
status of the Data–Source Selection pins, data may be routed to the outputs
either from the flip–flops or transmitted real–time from the inputs (see
Function Table and Application Information).
The Output Enable and the Direction pins control the transceiver’s
function. Bus A and Bus B cannot be routed as outputs to each other
simultaneously, but can be routed as inputs to the A and B flip–flops. Also,
the A and B flip–flops can be routed as outputs to Bus A and Bus B.
Additionally, when either or both of the ports are in the high–impedance
state, these I/O pins may be used as inputs to the D flip–flops for data
storage.
The user should note that because the clocks are not gated with the
Direction and Output Enable pins, data at the A and B ports may be clocked
into the storage flip–flops at any time.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 780 FETs or 195 Equivalent Gates
LOGIC DIAGRAM
A
DATA
PORT
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
OUTPUT ENABLE
DIRECTION
FLIP–FLOP A–TO–B CLOCK
CLOCKS B–TO–A CLOCK
DATA SOURCE A–TO–B SOURCE
SELECTION
INPUTS B–TO–A SOURCE
21
3
1
23
2
22
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
B
DATA
PORT
PIN 24 = VCC
PIN 12 = GND
MC54/74HC646
24
1
J SUFFIX
CERAMIC PACKAGE
CASE 758–02
24
1
24
1
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
DW SUFFIX
SOIC PACKAGE
CASE 751E–04
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
A–TO–B
CLOCK
A–TO–B
SOURCE
DIRECTION
A0
1
2
3
4
24 VCC
23
B–TO–A
CLOCK
22 B–TO–A
SOURCE
21 OUTPUT ENABLE
A1 5
20 B0
A2 6
19 B1
A3 7
18 B2
A4 8
17 B3
A5 9
16 B4
A6 10
15 B5
A7 11
14 B6
GND 12
13 B7
10/95
© Motorola, Inc. 1995
3–1 REV 6
1 page  
MC54/74HC646
FUNCTION TABLE — HC646
Control Inputs
Data Port Status
Storage Flip–
Flop States
Output
Enable
H
Direc–
tion
X
A–to–B
Clock
H, L,
B–to–A
Clock
H, L,
A–to–B
Source
X
B–to–A
Source
X
A
Input:
X
B
Input:
X
QA
no change
QB
no change
Description of Operation
The output functions of the A and B
ports are disabled
LX
HX
XXXL
XH
L
H
X
X
X The ports may be used as inputs to
X the storage flip–flops. Data at the in-
L puts are clocked into the flip–flops
H with the rising edge of the Clocks.
LH
Input: Output:
The output mode of the B data port is
enabled and behaves according to
the following logic equation:
B = [A • (A–to–B Source)]
+ [QA • (A–to–B Source)]
H, L,
X*
L
X
L
L no change no change 1.) When A–to–B Source is low, the
H H no change no change data at the A data port are dis-
played at the B data port. The
states of the storage flip–flops are
not affected.
H X X QA no change no change 2.) When A–to–B Source is high, the
states of the A storage flip–flops are
displayed at the B data port.
X* L X L L
HH
L no change 3.) When A–to–B Source is low, the
H
no change
data at the A data port are clocked
into the A storage flip–flops by a ris-
ing–edge signal on the A–to–B
Clock.
H
LL
X* H, L,
X
X L QA
H QA
L no change 4.) When A–to–B Source is high, the
H
no change
data at the A data port are clocked
into the A storage flip–flops by a ris-
ing–edge signal on the A–to–B
Clock. The states, QA, of the stor-
age flip–flops propagate directly to
the B data port.
Output: Input:
The output mode of the A data port is
enabled and behaves according to
the following logic equation:
A = [B • (B–to–A Source)]
+ [QB • (B–to–A Source)]
L L L no change no change 1.) When B–to–A Source is low, the
H H no change no change data at the B data port are dis-
played at the A data port. The
states of the storage flip–flops are
not affected.
X H QB X no change no change 2.) When B–to–A Source is high, the
states of the B storage flip–flops are
displayed at the A data port.
X*
X
L
L
L no change
L 3.) When B–to–A Source is low, the
H
H no change
H
data at the B data port are clocked
into the B storage flip–flops by a ris-
ing–edge signal on the B–to–A
Clock.
X
H
QB
L no change
L 4.) When B–to–A Source is high, the
QB
H no change
H
data at the B data port are clocked
into the B storage flip–flops by a ris-
ing–edge signal on the B–to–A
Clock. The states, QB, of the stor-
age flip–flops propagate directly to
the A data port.
* The clocks are not internally gated with either the Output Enables or the Source inputs. Therefore, data at the A and B ports may be clocked into
the storage flip–flops at any time.
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
5 Page 
OUTPUT ENABLE
DIRECTION
DATA PORT A
DATA PORT A
DATA PORT B
DATA PORT B
50%
tPHZ
90%
tPLZ
10%
tPZH
50%
tPZL
50%
tPZH
50%
tPZL
50%
tPHZ
90%
tPLZ
10%
DATA PORT A = INPUT
DATA PORT B = OUTPUT
DATA PORT A = OUTPUT
DATA PORT B = INPUT
Figure 7.
MC54/74HC646
VCC
GND
VCC
GND
VOH
HIGH IMPEDANCE
HIGH IMPEDANCE
VOL
VOH
HIGH IMPEDANCE
HIGH IMPEDANCE
VOL
OUTPUT ENABLE
OUTPUT A OR B
OUTPUT A OR B
50%
tPZL tPLZ
50%
tPZH tPHZ
50%
Figure 8.
VCC
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 9. Test Circuit
* Includes all probe and jig capacitance
Figure 10. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
3–11
MOTOROLA
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MC74HC646.PDF ] | |
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